초록 ▼

A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to

A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel. The metal layer is polished with an alkaline solution to remove the metal layer that does not lie within the interconnect chapel to form an interconnect. The present invention further includes a method of forming an interconnect over a silicon nitride layer. The silicon nitride layer is deposited over a semiconductor substrate and patterned to form a contact opening that is subsequently filled with a conductive material. A metal layer is deposited on the patterned silicon nitride layer and the contact plug and patterned to form the interconnect such that all of the interconnect lies on the contact plug and part of the patterned silicon nitride layer.

대표청구항 ▼

A method of forming an interconnect on a semiconductor substrate comprising the steps of: depositing a first dielectric layer on said substrate; patterning said first dielectric layer to form a patterned first dielectric layer having a first opening; filling said first opening with a conductive plug

A method of forming an interconnect on a semiconductor substrate comprising the steps of: depositing a first dielectric layer on said substrate; patterning said first dielectric layer to form a patterned first dielectric layer having a first opening; filling said first opening with a conductive plug; depositing a second dielectric layer over said patterned first dielectric layer and said conductive plug; patterning said second dielectric layer to form a patterned second dielectric layer having an interconnect channel, wherein part of said interconnect channel lies over at least part of said conductive plug, and wherein at least the upper portion of said first dielectric layer has a lower etch rate than said second dielectric layer such that said first dielectric layer acts as an etch stop; depositing a barrier layer over said patterned second dielectric layer and within said interconnect channel; depositing a metal layer over said barrier layer; polishing said substrate with a polishing solution to remove that portion of said barrier and metal layers that lie on said patterned second dielectric layer to form said interconnect within said interconnect channel; and depositing a diffusion barrier layer over said patterned second dielectric layer and said interconnect.