[특허]Low power data translation circuit and method of operation

[미국특허] Low power data translation circuit and method of operation 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G11C-015/00
출원번호	US-0506305 (1995-07-24)
발명자 / 주소	Maguire Jeffrey E. (Austin TX)
출원인 / 주소	Motorola (Schaumburg IL 02)
인용정보	피인용 횟수 : 36 인용 특허 : 4

초록 ▼

A low power circuit (10) for translating logical addresses or input data to corresponding physical addresses or output data respectively. The circuit (10) includes an input latch (12), content addressable memory (CAM) (14), random access memory (RAM) (16), output latch (18), and comparator (20). The input latch (12) receives the logical address (22) and stores the logical address for at least one comparison cycle. The CAM (14) receives the logical address (22) and produces a corresponding match signal. The RAM (16) receives the corresponding match signal and produces the corresponding physical address (28). The output latch (18) receives the corresponding physical address (28) and stores the value for at least one clock cycle. The comparator (20) enables the CAM (14) and/or the RAM (16) operation only when the previous logical address does not match the current logical address (22). The corresponding physical address (28) remains in the output latch (18) until such time as a new logical address (22) or input data is provided to the low power circuit (10).

대표청구항 ▼

A low power circuit for translating a logical address to a corresponding physical address, the low power circuit comprising: an input latch for receiving a logical address; a content addressable memory (CAM), for receiving the logical address and producing a corresponding match signal when the logical address matches an entry stored in the CAM; a random access memory operably coupled to the content addressable memory, the random access memory stores a plurality of physical adresses, and upon receipt of an enable signal and the corresponding match signal, the random access memory produces a corresponding physical address; an output latch operable coupled to the random access memory, wherein the output latch stores the corresponding physical address; and a comparator operably coupled to the input latch, the content addressable memory, and the random access memory, the comparator receives the logical address, and a prior logical address, wherein the comparator compares the logical address with the prior logical address, and the comparator asserts the enable signal when the logical address does not match the prior logical address, wherein the random access memory is maintained in a low power consumption state if the enable signal is de-asserted.

이 특허에 인용된 특허 (4) 인용/피인용 타임라인 분석

Horst Robert W. (Champaign IL) Yamamoto I. Ko (Santa Clara CA) Shah Ajay K. (San Jose CA), Apparatus and method for reading, writing, and refreshing memory with direct virtual or physical access.
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Oldham Harry E. (Swavesey GB3), Data memory and method of reading a data memory.
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Gutierrez Joseph A. (Austin TX) Moyer William C. (Dripping Springs TX) Ho Yui K. (Austin TX), Data processor with shared control and drive circuitry for both breakpoint and content addressable storage devices.
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Nguyen De H. (Milpitas CA) Chu Raymond M. (Saratoga CA), Logically disconnectable virtual-to-physical address translation unit and method for such disconnection.
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이 특허를 인용한 특허 (36) 인용/피인용 타임라인 분석

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Mathews, Gregory S.; Grochowski, Edward T.; Chung, Chih-Hung, Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end.
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Pontius, Timothy A.; Ehmann, Gregory E., Binary data memory design with data stored in low-power sense.
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Shigeyuki Hayakawa JP; Masashi Hirano JP, CAM Cell Circuit having decision circuit.
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Ross Mark, CAM match line precharge.
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Subramani Kengeri ; Steve Lim, Charge shared match line differential generation for CAM.
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Singh, Mandeep; McIntyre, David Hugh; Ngo, Hung Phuong, Conditionally precharged dynamic content addressable memory.
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Srinivasan, Varadarajan; Nataraj, Bindiganavale S.; Khanna, Sandeep, Content addressable memory having dynamic match resolution.
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Forin, Alessandro, Credit-based methods and systems for controlling data flow between a sender and a receiver with reduced copying of data.
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Kim, Jin kyu; Kim, Min young; Kim, Jang hwan; Yoon, Song ho, Data processing apparatus and method for flash memory.
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Huang Eddy C., Dynamic comparator with improved pre-charge/set-up time.
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Bunce, Paul A.; Davis, John D.; Plass, Donald W., High speed latch and compare function.
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Fred J. Towler ; Reid A. Wistort, Low power CAM match line circuit.
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Slavin, Keith R., Low power, hash-content addressable memory architecture.
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Rangarajan, Anand; Venkatachary, Srinivasan, Method and device for scalable multiple match extraction from search data.
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Luick,David A., Method and system for reducing power consumption in a computing device when the computing device executes instructions in a tight loop.
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Shadan H. Victor ; Nigam Anurag, Mutually controlled match-line-to-word-line transfer circuit.
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Miyatake Hisatada,JPX ; Tanaka Masahiro,JPX ; Mori Yohtaro,JPX, Pre-charging circuit and method for a word match line of a content add ressable memory (CAM).
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Khanna, Sandeep, Selective match line control circuit for content addressable memory array.
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Lee Woo Young,KRX, Semiconductor memory device having a plurality of memory blocks.
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Keller, James B.; Sharma, Puneet; Schakel, Keith R.; Matus, Francis M., Training line predictor for branch targets.
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McCombs, Edward M.; Kamdar, Chetan C.; Miller, William V., Translation lookaside buffer structure including an output comparator.
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Cong Khieu ; Xin Liu ; Der-ren Chu ; Lan Lee, Translation-lookaside buffer with current tracking reference circuit.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Low power data translation circuit and method of operation 원문보기