초록 ▼

The optimum SPS receiver is described that allows to optimize the demodulation of the unknown W-code generated by the Global Positioning System (GPS). The assumed timing and the spectrum structure of W-code are used for selecting the optimum digital filter that optimizes the signal-to-noise (STN) ra

The optimum SPS receiver is described that allows to optimize the demodulation of the unknown W-code generated by the Global Positioning System (GPS). The assumed timing and the spectrum structure of W-code are used for selecting the optimum digital filter that optimizes the signal-to-noise (STN) ratio of the received satellite signals.

대표청구항 ▼

A system for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVER, said system comprising: a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, and

A system for optimum correlation processing of L1 and L2 signals received from a SPS satellite by a SPS RECEIVER, said system comprising: a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, and for receiving an unknown Y code modulated on L2 carrier frequency signal from at least one satellite; wherein said received L1 , and L2 signals contain propagation noise; and wherein said Y code comprises a known P code and an unknown W code; and at least one DIGITAL CHANNEL PROCESSING MEANS for: (1) locally generating replica of said C/A code modulated on L1 carrier frequency signal; (2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal do not contain propagation noise; (3) extracting of an estimate of said Y code from said L1 signal, and from said L2 signal, wherein said estimate signals contain propagation noise; (4) correlating a locally generated replica of C/A code with the received L1 code for obtaining an estimate of L1 group delay (L1 pseudo-range) and L1 carrier phase; (5) removing said P code from said locally extracted estimate of said L1 Y code to obtain a locally extracted estimate of said L1 W code; (6) removing said P code from said locally extracted estimate of said L2 Y code to obtain a locally extracted estimate of said L2 W code; and (7) correlating said locally extracted estimate of said L1 W code with said locally extracted estimate of said L2 W code to obtain relative offset in group delay between L1 and L2 signals and for obtaining an independent estimate of L2 carrier phase; and wherein said RECEIVING MEANS further comprises: a dual frequency patch ANTENNA MEANS for receiving said L1 and L2 satellite signals; a FILTER/LNA MEANS conductively connected to said ANTENNA MEANS for performing filtering and low noise amplification of said L1 and L2 signals, wherein said FILTER/LNA determines the noise/signal ratio of the received signals L1 and L2; a DOWNCONVERTER MEANS conductively connected to said FILTER/LNA MEANS for mixing and converting said L1 and L2 signals; and an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming, said converted L1 and L2 signals into digitally sampled quadrature versions of L1 and L2 signals (IL1 , QL1 , IL2 , QL2 ); a MASTER OSCILLATOR MEANS; and a FREQUENCY SYNTHESIZER MEANS conductively connected to said MASTER OSCILLATOR MEANS, to said IF PROCESSOR MEANS, to said DOWNCONVERTER MEANS, and to at least one said DIGITAL, CHANNEL PROCESSING MEANS, wherein said FREQUENCY SYNTHESIZER MEANS generates several timing signals; and wherein said IF PROCESSOR MEANS further comprises: a first POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L1 signal into two signals; a second POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L2 signal into two signals; a first MULTIPLIER MEANS for multiplying said L1 signal with an inphase (I) version of said second LO2 signal to produce an IL1 signal; a second MULTIPLIER MEANS for multiplying said L1 signal with a quadrature (Q) version of said second LO2 signal to produce a QL1 signal; a third MULTIPLIER MEANS for multiplying said L2 signal with an inphase (I) version of said 2-nd LO2 signal to produce an IL2 signal a fourth MULTIPLIER MEANS for multiplying said L2 signal with a quadrature (Q) version of said 2-nd LO2 signal to produce a QL2 signal; a first AMPLIFIER MEANS connected to said first MULTIPLIER MEANS for amplifying said IL1 signal; a second AMPLIFIER MEANS connected to said second MULTIPLIER MEANS for amplifying said QL1 signal; a third AMPLIFIER MEANS connected to said third MULTIPLIER MEANS for amplifying said IL2 signal; a fourth AMPLIFIER MEANS connected to said fourth MULTIPLIER MEANS for amplifying said QL2 signal; a first one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said first AMPLIFIER MEANS for performing 1-bit quantization operation on said IL1 signal; a second one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said second AMPLIFIER MEANS for performing 1-bit quantization operation on said QL1 signal; a third one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said third AMPLIFIER MEANS for performing 1-bit quantization operation on said IL2 signal; a fourth one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said fourth AMPLIFIER MEANS for performing 1-bit quantization operation on said QL2 signal; a first FLIP-FLOP MEANS (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1at sampling clock (SCLK) rate; a second FLIP-FLOP MEANS (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2at sampling clock (SCLK) rate; a third FLIP-FLOP MEANS (FF3) connected to said third one-bit A/D CONVERTER for sampling said IL2 signal, wherein said sampling operation is performed by clocking said IL2 signal through said FF3 at sampling clock SCLK) rate; and a fourth FLIP-FLOP MEANS (FF4) connected to said fourth one-bit A/D CONVERTER for sampling said QL2 signal, wherein said sampling operation is performed by clocking said QL2 signal through said FF4 at sampling clock (SCLK) rate; and wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises: an L1 TRACKER MEANS for tracking L1 C/A code when Y code is ON and for tracking L1 P code when Y code is OFF; an L2 TRACKER MEANS connected to said L1 TRACKER MEANS for tracking an enhanced cross correlated W code when Y code is ON and for tracking L2 P code when Y code is OFF; and a MICROPROCESSOR MEANS system connected to said L1 TRACKER MEANS and to said L2 TRACKER MEANS; wherein said L1 TRACKER MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and wherein said L2 TRACKER MEANS is fed by digitized inphase I L2 and quadrature QL2 of L2 signal outputted by said IF PROCESSOR MEANS; and wherein each said L1 and L2 TRACKER MEANS are synchronously clocked by said SCLK signal and synchronously referenced by said MSEC signal to local reference time; said SCLK and MSEC signals being outputted by said FREQUENCY SYNTHESIZER MEANS; and wherein said L2 TRACKER MEANS when Y code is ON is fed from said L1 TRACKER MEANS by generated by said L1 TRACKER MEANS three signals: L1 P code, filtered estimate of L1 W code, and C/A code epoch (EP code); and wherein said MICROPROCESSOR MEANS system is fed by output signals from said L1 TRACKER MEANS and said L2 TRACKER MEANS; and wherein said L1 TRACKER MEANS and said L2 TRACKER MEANS are fed by control signal from said MICROPROCESSOR MEANS; and wherein said L1 TRACKER MEANS further comprises: a CODE GENERATOR MEANS for providing a locally generated replica of C/A code and P code; a MULTIPLEXER MEANS 1 connected to said CODE GENERATOR MEANS for selecting a locally generated code C/A when Y code is ON and for selecting a locally generated P code when Y code is OFF, said MULTIPLEXER MEANS 1 being controlled by said MICROPROCESSOR MEANS system; a carrier numerically controlled oscillator (CARRIER NCO MEANS 1) connected to said MULTIPLEXER MEANS 1; a CARRIER MIXER MEANS 1 connected to said CARRIER NCO MEANS 1 for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and Q L1 signals having carrier frequency with outputted by said CARRIER NCO MEANS 1 inphase and quadrature components of digital carrier; wherein said CARRIER MIXER MEANS 1 outputs inphase IL1 and quadrature Q L1 signals having zero carrier frequency: a CODE MIXER MEANS 1 connected to said CARRIER MIXER MEANS 1, connected to said CODE GENERATOR MEANS and connected to said CARRIER NCO MEANS 1 for code correlating said CARRIER MIXER MEANS 1 output signals with said locally generated replica of C/A code; wherein when said L1 TRACKER MEANS\s carrier tracking loop is closed via said CARRIER NCO MEANS 1 the input to said CODE MIXER MEANS 1 represents the satellite signal L1 C/A code; and wherein said CODE MIXER MEANS 1 performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function; a block CORRELATORS MEANS 1 connected to said CODE MIXER MEANS 1 for integrating said early, punctual and late samples of said autocorrelation function; wherein said CORRELATORS MEANS 1 output signal is fed to said MICROPROCESSOR MEANS system at a rate of L1 C/A code epoch, and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS 1 output signal to develop feedback signals for the carrier tracking loop and for the code tracking loop; a code numerically controlled oscillator (CODE NCO MEANS) connected to said block CORRELATORS MEANS 1 and connected to said CODE GENERATOR MEANS for providing a clocking signal at C/A code rate and for providing a clocking signal at P code rate, said C/A code clocking rate and said P code clocking rate driving said CODE GENERATOR MEANS; said CODE NCO MEANS also providing a mechanism for aligning said locally generated replica of C/A code with said incoming satellite C/A code; a CODE MIXER MEANS 2 connected to said CARRIER MIXER MEANS 1 and connected to said CODE GENERATOR MEANS, said CARRIER MIXER MEANS 1 outputting an estimate of L1 Y code as an input to said CODE MIXER MEANS 2, said CODE GENERATOR MEANS outputting said local replica of known L1 P code as input to said CODE MIXER MEANS 2, wherein said CODE MIXER MEANS 2 removes known L1 P code from said estimate of L1 Y code and outputs an estimate of L1 W code; a DIGITAL DELAY MEANS 1 connected to said CODE MIXER MEANS 2 for delaying under said MICROPROCESSOR MEANS system control said L1 W code estimate; a DIGITAL FILTER MEANS 1 connected to said DIGITAL DELAY MEANS 1 for reducing the bandwidth of said L1 W code estimate; wherein said delayed and filtered L1 W code estimate is sent for processing to said L2 TRACKER MEANS; a DIGITAL DELAY MEANS 2 connected to said CODE GENERATOR MEANS for delaying said P code output from said CODE GENERATOR MEANS, wherein said delayed P code is sent to said L2 TRACKER MEANS; and a RESOLVER MEANS connected to said CARRIER NCO MEANS 1 for toggling the digital delay between the two delays in the DIGITAL DELAY 1 and in the DIGITAL DELAY 2, wherein the resulting delay is the average of the relative time spent on each said delay; and wherein said L1 C/A code epoch (EP) is sent to said L2 TRACKER MEANS; and wherein said DIGITAL FILTER MEANS 1 further comprises a finite impulse response (FIR) DIGITAL FILTER 1; and wherein said FIR DIGITAL FILTER 1 performs the enhanced cross correlation operation by matching the observed W-code spectrum and by optimizing the signal-to-noise (STN) ratio of the cross-correlation process.