초록 ▼

A linear systolic array of computation cells, each cell having several vector rotation stages. These stages are programmable to provide efficient implementation of a variety of matrix algorithms. All data movement between cells is via parameterized data packets, and the full linear systolic array is

A linear systolic array of computation cells, each cell having several vector rotation stages. These stages are programmable to provide efficient implementation of a variety of matrix algorithms. All data movement between cells is via parameterized data packets, and the full linear systolic array is completely data flow driven at the packet level. Physical computation cells can be mapped to act as one or more logical computation cells, allowing a small array to function logically as a larger array through a logical folding. This mapping also allows defective cells to be bypassed for fault tolerance. The array can be used to compute adaptive weights in digital beamforming radar applications.

대표청구항 ▼

A programmable processor system for performing extremely high throughput matrix arithmetic operations on linear systems of equations in real time, said processor system comprising a linear systolic array of computation cells, each cell comprising a plurality of vector rotation stages, and programmab

A programmable processor system for performing extremely high throughput matrix arithmetic operations on linear systems of equations in real time, said processor system comprising a linear systolic array of computation cells, each cell comprising a plurality of vector rotation stages, and programmable means responsive to configuration data to configure respective cells according to said configuration data, said configuration data determining which cells are operational during said matrix arithmetic operations, where in said linear array is programmable in operational cell length, wherein said computation cells are programmably arranged in a folded arrangement wherein data is passed successively through a programmable under of said cells in a first direction and back through said cells in a second direction in a time interleaved manner, and wherein said cells further include programmable latency delay means for delaying transfer of data between cells in order to achieve proper interleaving of said data for different operational array lengths, said configuration data further includes latency programming data, said programmable latency delay means responsive to said latency programming data to set said delay means in accordance with said latency programming data.