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A data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A first set of bus parameters functions as a memory bus for transfers to and from main memory, a second se

A data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A first set of bus parameters functions as a memory bus for transfers to and from main memory, a second set of bus parameters functions as an I/O bus for I/O device transfers and a third set of bus parameters functions as a video bus for transfers to a video display. Each set of bus parameters has different timing selected to maximize transfers for the particular bus function (main memory, I/O, video or other) implemented by the bus parameters.

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A data processing system comprising, a processor, a plurality of external bus devices connected to the processor for communicating with the processor at different times, said bus devices operating with different timing parameters that include different information transfer rates associated with diff

A data processing system comprising, a processor, a plurality of external bus devices connected to the processor for communicating with the processor at different times, said bus devices operating with different timing parameters that include different information transfer rates associated with different bus bandwidths, a plurality of special-purpose buses each connected to the processor and to one of the external devices and each operating at a different bus bandwidth corresponding to the bus bandwidth associated with the bus device to which it is connected, a single common bus connecting the plurality of external bus devices to the plurality of special-purpose buses, and bus processing means for controlling the bus bandwidth of the common bus, to correspond to the bus bandwidth associated with the external bus device that is communicating with the processor at any one of said different times.