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High density lead-on-package fabrication method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
  • H05K-003/30
출원번호 US-0497565 (1995-06-30)
발명자 / 주소
  • Burns Carmen D. (Austin TX)
출원인 / 주소
  • Staktek Corporation (Austin TX 02)
인용정보 피인용 횟수 : 77  인용 특허 : 61

초록

The present invention provides a method and apparatus for fabricating thermally and electrically improved electronic integrated circuits by laminating one or more lead frames to a standard integrated circuit package such as, for example, a thin small outline package (TSOP). The lead frame laminated

대표청구항

A method of forming a warp-resistant integrated circuit package, comprising the steps off: providing an integrated circuit package, said package having an upper and a lower major exterior planar surface, said package including an integrated circuit element at least substantially encapsulated within

이 특허에 인용된 특허 (61)

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  8. Ross Milton I. (400 College Ave. Haverford PA 19041), Encapsulated electronic circuit device, and method and apparatus for making same.
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  36. Conru H. Ward (Essex Junction VT) Irish Gary H. (Jericho VT) Pakulski Francis J. (Shelburne VT) Slattery William J. (Essex Junction VT) Starr Stephen G. (Essex Junction VT) Ward William C. (Burlingto, Planarized thin film surface covered wire bonded semiconductor package.
  37. Katsumata Akio (Yokohama JPX) Hirata Seiichi (Yokosuka JPX) Fujieda Shinetsu (Kawasaki JPX) Shimozawa Hiroshi (Yokohama JPX), Plastic molded semiconductor device having waterproof cap.
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  40. Dran Maurice (Paris FRX) Dages Daniel (Les Mureaux FRX) Le Gravier Serge (Orleans FRX), Process for manufacture of solar photocell panels and panels obtained thereby.
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  46. Konishi Akira (Kyoto JPX) Wakano Teruo (Kyoto JPX), Semiconductor device and its manufacture.
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  48. Cady James W. (Austin TX), Simulcast standard multichip memory addressing system.
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  50. Mueller Wolfgang R. (Wappingers Falls NY) Spencer ; II Gwynne W. (Poughkeepsie NY), Stacked double density memory module using industry standard memory chips.
  51. Quattrini Victor L. (Westford MA) Fisher Edwin P. (Abington MA), Surface mounted multilayer memory printed circuit board.
  52. Holzinger Steven T. (Tempe AZ) Barker Larry W. (Chandler AZ), Tape automated bonding and method of making the same.
  53. Woodman John K. (601 Mystic La. Foster City CA 94404), Three dimensional integrated circuit package.
  54. Davidson Howard L. (San Carlos CA), Three dimensional packaging arrangement for computer systems and the like.
  55. Berhold G. Mark (7752 Steffensen Dr. Salt Lake City UT 84121), Three-dimensional circuit component assembly and method corresponding thereto.
  56. Burns Carmen D. (Austin TX), Ultra high density integrated circuit packages method.
  57. Burns Carmen D. (Austin TX) Roane Jerry (Austin TX) Cady James W. (Austin TX), Ultra high density integrated circuit packages method.
  58. Burns Carmen D. (Austin TX), Ultra high density integrated circuit packages method and apparatus.
  59. Burns Carmen D. (Austin TX), Ultra high density modular integrated circuit package.
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  61. Burns Carmen D. (Austin TX) Cady James W. (Austin TX) Roane Jerry M. (Austin TX) Troetschel Phillip R. (Buda TX), Warp-resistent ultra-thin integrated circuit package fabrication method.

이 특허를 인용한 특허 (77)

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  6. Szewerenko, Leland; Partridge, Julian; Orris, Ron, Circuit module having force resistant construction.
  7. Szewerenko,Leland; Partridge,Julian; Orris,Ron, Circuit module having force resistant construction.
  8. Szewerenko, Leland; Partridge, Julian; Lieberman, Wayne; Goodwin, Paul, Circuit module turbulence enhancement systems and methods.
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  11. Wehrly, Jr.,James Douglas, Composite core circuit module system and method.
  12. James Douglas Wehrly, Jr., Contact member stacking system and method.
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  14. Cady, James W.; Goodwin, Paul, Die module system.
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  16. Wehrly, Jr., James Douglas; Goodwin, Paul; Rapport, Russell, Flex circuit constructions for high capacity circuit module systems and methods.
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