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High tensile nitride layer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
출원번호 US-0660734 (1996-06-06)
발명자 / 주소
  • Brigham Lawrence N. (Beaverton OR) Lee Yung-Huei (Sunnyvale CA) Chau Robert S. (Beaverton OR) Cotner Raymond E. (Beaverton OR)
출원인 / 주소
  • Intel Corporation (Santa Clara CA 02)
인용정보 피인용 횟수 : 39  인용 특허 : 19

초록

An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8×109 dynes/cm-2 and -3×1010 dynes/cm-2. The insulating layer can further comprise a do

대표청구항

A method of forming a semiconductor device, said method comprising the steps of: forming a transistor on said semiconductor substrate, said transistor having at least one silicide region; forming a doped oxide layer on said transistor including said silicide layer; forming a nitride layer having a t

이 특허에 인용된 특허 (19)

  1. Joshi Rajiv V. (Yorktown Heights NY), Graded oxide/nitride via structure and method of fabrication therefor.
  2. Richman Paul (St. James NY), Last-stage programming of semiconductor integrated circuits including selective removal of passivation layer.
  3. Moslehi Mehrdad M. (Dallas TX), Low-RC multi-level interconnect technology for high-performance integrated circuits.
  4. Ogawa Hisashi (Katano JPX) Naito Yasushi (Toyonaka JPX) Fukumoto Masanori (Osaka JPX), Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact windo.
  5. Madokoro Shoji (Tokyo JPX), Method for forming an electrode layer by a laser flow technique.
  6. Kobayashi Masato (Tokyo JPX) Yamaguchi Yoichi (Tokyo JPX), Method for forming silicon nitride film.
  7. Barber Jeffrey R. (Pittsburgh PA) Breiten Charles P. (Manassass VA) Stanasolovich David (Manassas VA) Theisen Jacob F. (Manassas VA), Method for making borderless contacts.
  8. Thakur Randhir P. S. (Boise ID), Method for optimizing thermal budgets in fabricating semconductors.
  9. Thakur Randir P. S. (Boise ID) Gonzalez Fernando (Boise ID), Method for optimizing thermal budgets in fabricating semiconductors.
  10. Bryant Frank R. (Denton TX) Waters John L. (Carrollton TX), Method of forming tunneling diffusion barrier for local interconnect and polysilicon high impedance device.
  11. Gargini Paolo (Palo Alto CA) Beinglass Israel (Santa Clara CA) Ahlquist Norman (Menlo Park CA), Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate.
  12. Yau Leopoldo D. (Portland OR) Chen Shih-ou (Fremont CA) Lin Yih S. (Beaverton OR), Method of making a silicon nitride resistor using plasma enhanced chemical vapor deposition.
  13. Haluska Loren A. (Midland MI) Michael Keith W. (Midland MI) Tarhay Leo (Sanford MI), Multilayer ceramics from silicate esters.
  14. Yokoi Katsuyuki (Shizuoka JPX) Suga Shigeru (Shizuoka JPX) Fujioka Toshio (Shizuoka JPX), Plasma vapor deposition of an improved passivation film using electron cyclotron resonance.
  15. Raby Joseph S. (W. Melbourne FL), Process using tungsten for multilevel metallization.
  16. Wei Che-Chia (Plano TX) Tang Thomas E. (Dallas TX) Bohlman James G. (Forney TX) Douglas Monte A. (Coppell TX), Selective silicidation process using a titanium nitride protective layer.
  17. Kyuragi, Hakaru; Oikawa, Hideo, Semiconductor device and process for manufacturing the same.
  18. Watanabe Tohru (Yokohama JPX) Okumura Katsuya (Yokohama JPX), Semiconductor substrate surface processing method using combustion flame.
  19. Chen Fusen (Dallas TX) Bryant Frank R. (Denton TX) Dixit Girish (Dallas TX), Structure and method for contacts in CMOS devices.

이 특허를 인용한 특허 (39)

  1. Chau Robert S., CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers.
  2. Chau, Robert S., CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers.
  3. Guarionex Morales ; Dawn Hopper ; Lu You, Electron microscopy sample having silicon nitride passivation layer.
  4. Chen, Chia-Chung; Huang, Chi-Feng; Lu, Tse-Hua, HVMOS reliability evaluation using bulk resistances as indices.
  5. Huang, Chi-Feng; Chen, Chia-Chung; Lu, Tse-Hua, HVMOS reliability evaluation using bulk resistances as indices.
  6. Arafa Mohamed ; Thompson Scott, Integrated circuit with borderless contacts.
  7. Arafa, Mohamed; Thompson, Scott, Integrated circuit with borderless contacts.
  8. Hoffmann,Thomas; Auth,Chris; Armstrong,Mark; Cea,Stephen, Integrated circuit with improved channel stress properties and a method for making it.
  9. Arafa Mohamed ; Thompson Scott, Integrated circuit with insulating spacers separating borderless contacts from the well.
  10. Zhu, Huilong; Zhong, Huicai; Leobandung, Effendi, Method and structure for forming self-aligned, dual stress liner for CMOS devices.
  11. Zhu,Huilong; Zhong,Huicai; Leobandung,Effendi, Method and structure for forming self-aligned, dual stress liner for CMOS devices.
  12. Lin, Cha Hsin; Pei, Zing Way; Tsai, Ming Jinn; Lu, Shing Chii, Method for fabricating semiconductor device.
  13. Dyer,Thomas W.; Yang,Haining, Method for forming self-aligned, dual silicon nitride liner for CMOS devices.
  14. Krishnan, Anand T.; Reddy, Vijay, Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process.
  15. Cheng-Che Lee TW; Chung-Chih Liu TW, Method for preventing native oxide growth during nitridation.
  16. Fitzgerald, Eugene A., Methods of fabricating contact regions for FET incorporating SiGe.
  17. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.
  18. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.
  19. Currie,Matthew T.; Hammond,Richard, Methods of forming reacted conductive gate electrodes.
  20. Eitan, Boaz, NROM fabrication method.
  21. Eitan, Boaz, NROM fabrication method.
  22. Lyons Christopher F., Nitride surface passivation for acid catalyzed chemically amplified resist processing.
  23. Eitan,Boaz; Maayan,Eduardo, Non-volatile memory cell and non-volatile memory device using said cell.
  24. Gerritsen, Eric; Baylac, Bruno; Basso, Marie-Thérèse, Process for forming a low resistivity titanium silicide layer on a silicon semiconductor substrate.
  25. Das John H. ; Thakur Randhir P. S., Process for forming thin dielectric layers in semiconductor devices.
  26. Braithwaite, Glyn; Hammond, Richard; Currie, Matthew, RF circuits including transistors having strained material layers.
  27. Currie, Matthew T.; Hammond, Richard, Reacted conductive gate electrodes.
  28. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.
  29. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.
  30. Currie, Matthew T.; Lochtefeld, Anthony J.; Hammond, Richard; Fitzgerald, Eugene A., Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.
  31. Currie, Matthew T.; Lochtefeld, Anthony J.; Hammond, Richard; Fitzgerald, Eugene A., Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.
  32. Currie, Matthew; Lochtefeld, Anthony; Hammond, Richard; Fitzgerald, Eugene, Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same.
  33. Currie,Matthew T.; Lochtefeld,Anthony J., Shallow trench isolation process.
  34. Hurley Kelly T., Silicon nitride deposition method.
  35. Kelly T. Hurley, Silicon nitride deposition method.
  36. Ting,Steve Ming, Strain enhanced ultra shallow junction formation.
  37. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures with elevated source/drain regions.
  38. Hsu Sheng Teng ; Yang Hongning ; Evans David R. ; Nguyen Tue ; Ma Yanjun, Stress-loaded film and method for same.
  39. Zhu,Huilong; Tessier,Brian L.; Zhong,Huicai; Li,Ying, Undercut and residual spacer prevention for dual stressed layers.
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