[특허]Method of making a semiconductor device having a silicide local interconnect

Method of making a semiconductor device having a silicide local interconnect 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/28
출원번호	US-0527893 (1995-09-14)
우선권정보	JP-0211279 (1993-08-26); JP-0078977 (1995-04-04)
발명자 / 주소	Hayashi Hiromi (Kawasaki JPX) Fushida Atsuo (Kawasaki JPX) Izawa Tetsuo (Kawasaki JPX) Katsube Masaki (Kawasaki JPX) Yamazaki Tatsuya (Kawasaki JPX)
출원인 / 주소	Fujitsu Limited (Kawasaki JPX 03)
인용정보	피인용 횟수 : 46 인용 특허 : 0

초록 ▼

On a semiconductor substrate with an exposed silicon region, a metal layer such as Co is deposited and a silicide layer is formed by heat treatment. Thereafter, a metal layer such as Ni and a silicon layer are deposited, and one of them is patterned. The metal layer and silicon layer are heated for silicification to form a local interconnect. A semiconductor device manufacturing method is provided which uses salicide technique and can form a local interconnect of good quality.

대표청구항 ▼

A method of manufacturing a semiconductor device comprising the steps of: forming a locally oxidized field oxide film by selectively oxidizing the surface of a silicon semiconductor substrate and defining a silicon surface surrounded at least partially by a locally oxidized field oxide film; depositing a film of a first metal on the substrate, the first metal film covering said silicon surface and said locally oxidized field oxide film; forming a silicon electrode pattern on said locally oxidized field oxide film; heating said substrate to silicify said first metal film with said silicon surface and form a first silicide layer and to silicify said first metal film with said silicon electrode pattern to form a second silicide layer; removing unreacted part of said first metal film; depositing a second metal film of a second metal, said second metal being different from said first metal and capable of forming said second silicide at a temperature where said first metal does not react with silicon, on the substrate, the second metal film covering said first silicide layer and said locally oxidized field oxide film; depositing a silicon film on said second metal film, and patterning said silicon film to form a silicon film pattern extending from a region over the surface of said first silicide layer, through a region over said locally oxidized field oxide film, to a region over said second silicide layer; heating said substrate to silicify said second metal film with said silicon film pattern and form a third silicide layer, without enhancing silicidation of said first silicide; and removing unreacted part of said second metal film.

이 특허를 인용한 특허 (46)

Lee, Whonchee; Hu, Yongjun Jeff, Composition for selectively etching against cobalt silicide.
상세보기
Jung Jong Wan,KRX, Forming a silicide in predetermined areas of a semiconductor device.
상세보기
Michael Mark W. ; Dawson Robert ; Fulford ; Jr. H. Jim ; Gardner Mark I. ; Hause Frederick N. ; Moore Bradley T. ; Wristers Derick J., Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance.
상세보기
Kim Sung-bong,KRX ; Kim Kyeong-tae,KRX, Integrated circuits including metal silicide contacts extending between a gate electrode and a source/drain region.
상세보기
Cantell Marc W. ; Lasky Jerome B. ; Line Ronald J. ; Murphy William J. ; Peterson Kirk D. ; Tiwari Prabhat, Integrated cobalt silicide process for semiconductor devices.
상세보기
Cantell, Marc W.; Lasky, Jerome B.; Line, Ronald J.; Murphy, William J.; Peterson, Kirk D.; Tiwari, Prabhat, Integrated cobalt silicide process for semiconductor devices.
상세보기
Mantl Siegfried,DEX, Layered structure with a silicide layer and process for producing such a layered structure.
상세보기
Ahn,Byung Chul; Lim,Byung Ho; Yoo,Soon Sung; Kim,Yong Wan; Ha,Young Hun, Liquid crystal display device having particular connections among drain and pixel electrodes and contact hole.
상세보기
En William G. ; Chan Darin A. ; Foote David K. ; Wang Fei ; Ngo Minh Van, Local interconnects for improved alignment tolerance and size reduction.
상세보기
Jun Young Kwon,KRX, Metal wire of semiconductor device and method for forming the same.
상세보기
Lee Whonchee ; Hu Yongjun Jeff, Method and composition for selectively etching against cobalt silicide.
상세보기
Lee, Whonchee; Hu, Yongjun Jeff, Method and composition for selectively etching against cobalt silicide.
상세보기
Lee, Whonchee; Hu, Yongjun Jeff, Method and composition for selectively etching against cobalt silicide.
상세보기
Lee,Whonchee; Hu,Yongjun Jeff, Method and composition for selectively etching against cobalt silicide.
상세보기
En William George ; Mehta Sunil ; Wang Fei ; Logie Stewart Gordon, Method and system for providing electrical insulation for local interconnect in a logic circuit.
상세보기
Murphy William J. ; Tiwari Prabhat, Method for depositing cobalt.
상세보기
Fang,Sunfei; Cabral, Jr.,Cyril; Dziobkowski,Chester T.; Ellis Monaghan,John J.; Lavoie,Christian; Luo,Zhijiong; Nakos,James S.; Steegen,An L.; Wann,Clement H., Method for forming self-aligned dual salicide in CMOS technologies.
상세보기
Yongjun Hu, Method for making a low resistivity electrode having a near noble metal.
상세보기
Hsu Sheng Teng, Method for manufacturing a CMOS self-aligned strapped interconnection.
상세보기
O'Brien Sean C., Method of fabricating self-aligned silicide.
상세보기
Nishihara, Shinji; Ikeda, Shuji; Hashimoto, Naotaka; Momiji, Hiroshi; Abe, Hiromi; Fukada, Shinichi; Suzuki, Masayuki, Method of fabricating semiconductor integrated circuit device.
상세보기
Nishihara, Shinji; Ikeda, Shuji; Hashimoto, Naotaka; Momiji, Hiroshi; Abe, Hiromi; Fukada, Shinichi; Suzuki, Masayuki, Method of fabricating semiconductor integrated circuit device.
상세보기
Nishihara, Shinji; Ikeda, Shuji; Hashimoto, Naotaka; Momiji, Hiroshi; Abe, Hiromi; Fukada, Shinichi; Suzuki, Masayuki, Method of fabricating semiconductor integrated circuit device.
상세보기
Nishihara,Shinji; Ikeda,Shuji; Hashimoto,Naotaka; Momiji,Hiroshi; Abe,Hiromi; Fukada,Shinichi; Suzuki,Masayuki, Method of fabricating semiconductor integrated circuit device.
상세보기
Nishihara,Shinji; Ikeda,Shuji; Hashimoto,Naotaka; Momiji,Hiroshi; Abe,Hiromi; Fukada,Shinichi; Suzuki,Masayuki, Method of fabricating semiconductor integrated circuit device with 99.99 wt% cobalt.
상세보기
Liang Kuei-Chang,TWX ; Yang Yu-Hao,TWX, Method of forming local interconnection of a static random access memory.
상세보기
Hause Fred N. ; Dawson Robert ; May Charles E., Method of forming uniform sheet resistivity salicide.
상세보기
Lin Xi-Wei, Method of improving process robustness of nickel salicide in semiconductors.
상세보기
Uno,Shouochi; Maekawa,Atsushi; Yunogami,Takashi; Tago,Kazutami; Nojiri,Kazuo; Machida,Shuntaro; Tokunaga,Takafumi, Method of manufacture of semiconductor integrated circuit.
상세보기
Hashimoto Koichi,JPX ; Hayashi Hiromi,JPX, Method of manufacturing a semiconductor device with local interconnect of metal silicide.
상세보기
Matsubara Yoshihisa,JPX, Method of manufacturing semiconductor device.
상세보기
Abbott, Todd; Tirvedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.
상세보기
Abbott, Todd; Trivedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.
상세보기
Abbott, Todd; Trivedi, Jigish D.; Violette, Mike; Dennison, Chuck, Method of selectively forming local interconnects using design rules.
상세보기
William G. En ; Darin A. Chan ; David K. Foote ; Fei Wang ; Minh Van Ngo, Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction.
상세보기
Kim Sung-bong,KRX ; Kim Kyeong-tae,KRX, Methods of fabricating integrated circuits including metal silicide contacts extending between a gate electrode and a source/drain region.
상세보기
Breil, Nicolas L.; Makela, Neal A.; Adusumilli, Praneet; Ferrer, Domingo A., Multiple step thin film deposition method for high conformality.
상세보기
Liu Wei-Hua ; Burnett David ; Swift Craig, Process for forming a semiconductor device having a conductive member that protects field isolation during etching.
상세보기
Nishihara, Shinji; Ikeda, Shuji; Hashimoto, Naotaka; Momiji, Hiroshi; Abe, Hiromi; Fukada, Shinichi; Suzuki, Masayuki, Process for producing semiconductor integrated circuit device.
상세보기
Breitwisch, Matthew J.; Brown, Jeffrey S.; Hook, Terence B.; Mann, Randy W.; Putnam, Christopher S.; Younus, Mohammad I., Selective silicide blocking.
상세보기
Breitwisch, Matthew J.; Brown, Jeffrey S.; Hook, Terence B.; Mann, Randy W.; Putnam, Christopher S.; Younus, Mohammad I., Selective silicide blocking.
상세보기
Asamura, Takeshi, Semiconductor device and method of making thereof.
상세보기
Hashimoto Koichi,JPX ; Hayashi Hiromi,JPX, Semiconductor device with local interconnect of metal silicide.
상세보기
Huang Jenn Ming,TWX, Silicide and salicide on the same chip.
상세보기
Ostermayr, Martin; Sarma, Chandrasekhar, Transistor level routing.
상세보기
Ostermayr, Martin; Sarma, Chandraserhar, Transistor level routing.
상세보기

내보내기 메뉴

내보내기 구분

파일저장
인쇄
메일전송

구성항목

기본정보
상세정보

관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC

저장형식

Text(ASCII format)
Excel format
PIAS분석(.xls)

메일정보

받는사람 (필수): @
보내는사람 (선택): @
제목
내용: KISTI 검색결과 이메일 서비스

안내

총 건의 자료가 검색되었습니다.

다운받으실 자료의 인덱스를 입력하세요. (1-10,000)

검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다.

데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요)

다운로드 파일은 UTF-8 형태로 저장됩니다.
파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오.

Text(ASCII format)
Excel format

AI-Helper ※ AI-Helper는 을 사용합니다.

AI-Helper

안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

연합인증

Method of making a semiconductor device having a silicide local interconnect 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

이 특허를 인용한 특허 (46)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Method of making a semiconductor device having a silicide local interconnect 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

이 특허를 인용한 특허 (46)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트