초록 ▼

A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss trac

A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package. Fabricated from two pieces of symmetrical printed circuit board material, this embodiment reduces ground bounce for IC current sourcing as well as IC current sinking, and provides approximately a 100% improvement in thermal dissipation as compared to prior art BGA packages.

대표청구항 ▼

A ball grid array (“BGA”) package for an integrated circuit (“IC”) having improved BGA package thermal and electrical characteristics, comprising: upper layer BGA package traces including a Vss trace, a Vdd trace, and a signal trace; lower layer BGA package traces at least a portion of which traces

A ball grid array (“BGA”) package for an integrated circuit (“IC”) having improved BGA package thermal and electrical characteristics, comprising: upper layer BGA package traces including a Vss trace, a Vdd trace, and a signal trace; lower layer BGA package traces at least a portion of which traces are in vertical alignment with a corresponding one of said upper layer BGA package traces; wherein regions of said lower layer BGA package traces are solderable to solder balls used to solder said BGA package to an underlying system printed circuit board; BGA core material disposed between said upper and lower layer BGA package traces; vias including a unitary-construction Vss via coupling said upper layer BGA Vss trace to a corresponding lower layer BGA Vss trace, a unitary-construction Vdd via coupling said upper layer BGA Vdd trace to a corresponding lower layer BGA Vdd trace, and a unitary-construction signal via coupling a said upper layer BGA signal trace to a corresponding lower layer BGA signal trace; and a BGA Vss plane, disposed intermediate said upper and lower layer BGA package traces and making electrical contact with said Vss via.