$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of bonding wafers having vias including conductive material 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/28
출원번호 US-0461951 (1995-06-05)
발명자 / 주소
  • Gaul Stephen Joseph (Melbourne FL)
출원인 / 주소
  • Harris Corporation (Palm Bay FL 02)
인용정보 피인용 횟수 : 291  인용 특허 : 0

초록

A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. The via has a sidewall oxide 131 and is filled with a conductive material such as metal or do

대표청구항

A method for fabricating surface mountable integrated circuits comprising the steps of: providing a device wafer of monocrystalline silicon material with first and second surfaces and with integrated circuits formed on the first surface of said device wafer; forming an oxide layer between the second

이 특허를 인용한 특허 (291)

  1. Gardner Mark I. ; Kadosh Daniel ; Duane Michael P., Air gap spacer formation for high performance MOSFETs.
  2. Andry, Paul S.; Cotte, John M.; Knickerbocker, John U.; Tsang, Cornelia K., Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers.
  3. Andry, Paul S.; Cotte, John M.; Knickerbocker, John U.; Tsang, Cornelia K., Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers.
  4. Cai, Jian; Wang, Qian; Liu, Ziyu; Hu, Yang, Bolometer and preparation method thereof.
  5. Adams, Scott G.; Davis, Tim, Boundary isolation for microelectromechanical devices.
  6. Chang, Hung-Pin; Hsu, Kuo-Ching; Chen, Chen-Shien; Chiou, Wen-Chih; Yu, Chen-Hua, Bump structure for stacked dies.
  7. Lin, Charles Wen Chyang, Bumpless flip chip assembly with solder via.
  8. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips and via-fill.
  9. Lin Charles Wen Chyang,SGX, Bumpless flip chip assembly with strips and via-fill.
  10. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips-in-via and plating.
  11. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips-in-via and plating.
  12. Farrar, Paul A.; Noble, Wendell P., Buried conductors.
  13. Forbes, Leonard, Capacitive techniques to reduce noise in high speed interconnections.
  14. Forbes,Leonard, Capacitive techniques to reduce noise in high speed interconnections.
  15. Bernstein, Kerry; Dalton, Timothy J.; Sprogis, Edmund J.; Stamper, Anthony K.; Williams, Richard Q., Chip-in-slot interconnect for 3D chip stacks.
  16. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Coaxial integrated circuitry interconnect lines, and integrated circuitry.
  17. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Compact system module with built-in thermoelectric cooling.
  18. Ahn,Kie Y.; Forbes,Leonard; Cloud,Eugene H., Compact system module with built-in thermoelectric cooling.
  19. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  20. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  21. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  22. Ahn Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  23. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  24. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  25. Oh, Tae Seok; Kim, Jong Hong, Coplanarity inspection system of package and method thereof.
  26. Forbes, Leonard; Ahn, Kie Y., Current mode signal interconnects and CMOS amplifier.
  27. Oh, HakJune; Kim, Jin-Ki; Pyeon, Hong Beom, Data storage and stackable chip configurations.
  28. Oh, HakJune; Kim, Jin-Ki; Pyeon, Hong Beom, Data storage and stackable configurations.
  29. Siniaguine, Oleg, Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture.
  30. H. Jim Fulford, Jr. ; Robert Dawson ; Fred N. Hause ; Basab Bandyopadhyay ; Mark W. Michael ; William S. Brennan, Dielectric having an air gap formed between closely spaced interconnect lines.
  31. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  32. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  33. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  34. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  35. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
  36. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking with leads extending along edges.
  37. Vieux-Rochaz, Line; Cuchet, Robert; Girard, Olivier, Electrical connection between two faces of a substrate and manufacturing process.
  38. Adams,Scott; Davis,Tim; Miller,Scott; Shaw,Kevin; Chong,John Matthew; Lee,Seung (Chris) Bok, Electrostatic actuator for microelectromechanical systems and methods of fabrication.
  39. Adams,Scott; Davis,Tim; Miller,Scott; Shaw,Kevin; Chong,John Matthew; Lee,Seung Bok (Chris), Electrostatic actuator for microelectromechanical systems and methods of fabrication.
  40. Charles W. C. Lin SG, Flip chip assembly with via interconnection.
  41. Charles W. C. Lin SG, Flip chip assembly with via interconnection.
  42. Gaul, Stephen Joseph; Hebert, Francois, Heat conduction for chip stacks and 3-D circuits.
  43. Farnworth Warren M., Hermetically sealed chip scale packages formed by wafer level fabrication and assembly.
  44. Bethoux, Jean-Marc; Letertre, Fabrice; Werkhoven, Chris; Radu, Ionut; Kononchuck, Oleg, Heterostructure for electronic power components, optoelectronic or photovoltaic components.
  45. Morgan William P., High density electronic circuit and process for making.
  46. Kie Y. Ahn ; Leonard Forbes ; Paul Farrar, High performance packaging for microprocessors and DRAM chips which minimizes timing skews.
  47. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability layered films to reduce noise in high speed interconnects.
  48. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.
  49. Andry, Paul S.; Cotte, John M.; Lofaro, Michael F.; Sprogis, Edmund J.; Tornello, James A.; Tsang, Cornelia K., High-yield method of exposing and contacting through-silicon vias.
  50. Dang, Bing; Knickerbocker, John U.; Liu, Yang, Integrated circuit (IC) test probe.
  51. Badehi, Avner, Integrated circuit device.
  52. Badehi, Avner, Integrated circuit device.
  53. Badehi, Avner, Integrated circuit device.
  54. Swan, Johanna M.; Mahajan, Ravi V.; Natarajan, Bala, Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
  55. Swan, Johanna M.; Natarajan, Bala; Chiang, Chien; Atwood, Greg; Rao, Valluri R., Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
  56. Swan,Johanna M.; Natarajan,Bala; Chiang,Chien; Atwood,Greg; Rao,Valluri R., Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
  57. Gardner Mark I. ; Spikes Thomas E. ; Paiz Robert, Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths.
  58. Ahn Kie Y., Integrated circuitry and methods of forming integrated circuitry.
  59. Kie Y. Ahn, Integrated circuitry having conductive passageway interconnecting circuitry on front and back surfaces of a wafer fragment.
  60. Oleg Siniaguine, Integrated circuits and methods for their fabrication.
  61. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  62. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  63. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  64. Lu,Szu Wei; Tzou,Jerry, Interconnect structure for semiconductor package.
  65. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Interlevel dielectric with air gaps to lessen capacitive coupling.
  66. Chang, Hung-Pin; Hsu, Kuo-Ching; Chen, Chen-Shien; Chiou, Wen-Chih; Yu, Chen-Hua, Isolation structure for stacked dies.
  67. Stephen P. Williams, Mechanically formed standoffs in a circuit interconnect.
  68. Pogge, H. Bernhard; Yu, Roy R., Metal filled through via structure for providing vertical wafer-to-wafer interconnection.
  69. Choi, Young-Soo; Kim, Gyu-Hyun, Metal line in semiconductor device.
  70. Choi, Young-Soo; Kim, Gyu-Hyun, Metal line in semiconductor device and method for forming the same.
  71. Farnworth Warren ; Kinsman Larry ; Moden Walter, Method and apparatus for a semiconductor package for vertical surface mounting.
  72. Farnworth, Warren; Kinsman, Larry; Moden, Walter, Method and apparatus for a semiconductor package for vertical surface mounting.
  73. Farnworth, Warren; Kinsman, Larry; Moden, Walter, Method and apparatus for a semiconductor package for vertical surface mounting.
  74. Farnworth, Warren; Kinsman, Larry; Moden, Walter, Method and apparatus for a semiconductor package for vertical surface mounting.
  75. Uzoh, Cyprian Emeka; Monadgemi, Pezhman; Caskey, Terrence; Ayatollahi, Fatima Lina; Haba, Belgacem; Woychik, Charles G.; Newman, Michael, Method and structures for heat dissipating interposers.
  76. Lin, Charles W. C., Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly.
  77. Nai-Chuan Chen TW; Bor-Jen Wu TW; Yuan-Hsin Tzou TW; Nae-Guann Yih TW; Chien-An Chen TW, Method for forming a semiconductor device having a metallic substrate.
  78. Kolb, Stefan; Winkler, Bernhard; Rangelow, Ivo; Blom, Hans-Olof; Bjurstroem, Johan, Method for forming a through via in a semiconductor element and semiconductor element comprising the same.
  79. Soh, Hyongsok, Method for interconnecting arrays of micromechanical devices.
  80. Kawano, Masaya; Soejima, Koji; Takahashi, Nobuaki, Method for manufacturing a semiconductor device.
  81. Halahan, Patrick B., Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity.
  82. Lee, Ki Yong; Ha, Seung Kweon, Method for manufacturing semiconductor package having improved bump structures.
  83. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Method for producing a protective structure.
  84. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Method for through silicon via structure.
  85. Kloster,Grant; Ramanathan,Shriram; Chen,Chin Chang; Fischer,Paul, Method of bonding semiconductor devices.
  86. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip.
  87. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a bumped compliant conductive trace to a semiconductor chip.
  88. Charles W. C. Lin SG; Cheng-Lien Chiang TW, Method of connecting a bumped conductive trace to a semiconductor chip.
  89. Lin, Charles W. C., Method of connecting a conductive trace and an insulative base to a semiconductor chip.
  90. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.
  91. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.
  92. Charles W. C. Lin SG, Method of connecting a conductive trace to a semiconductor chip.
  93. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip.
  94. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using a metal base.
  95. Lin,Charles W. C., Method of connecting a conductive trace to a semiconductor chip using conductive adhesive.
  96. Chiang, Cheng-Lien; Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching.
  97. Lin,Charles W. C.; Chiang,Cheng Lien, Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip.
  98. Haba, Belgacem; Mohammed, Ilyas, Method of fabricating stacked assembly including plurality of stacked microelectronic elements.
  99. Haba, Belgacem, Method of fabricating stacked packages with bridging traces.
  100. Kim, Sarah E.; List, R. Scott; Maveety, James G.; Myers, Alan M.; Vu, Quat T., Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips.
  101. Gardner Mark I. ; Kadosh Daniel ; Duane Michael P., Method of forming air gap spacer for high performance MOSFETS'.
  102. Chang, Hung-Pin; Hsu, Kuo-Ching; Chen, Chen-Shien; Chiou, Wen-Chih; Yu, Chen-Hua, Method of forming bump structure having tapered sidewalls for stacked dies.
  103. Tsai Ming-Hsing,TWX, Method of forming bumps for flip chip applications.
  104. Farrar, Paul A.; Noble, Wendell P., Method of forming buried conductors.
  105. Mashino, Naohiro, Method of forming through-hole or recess in silicon substrate.
  106. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a bumped terminal in a laminated structure for a semiconductor chip assembly.
  107. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly.
  108. Lin, Charles W. C., Method of making a pillar in a laminated structure for a semiconductor chip assembly.
  109. Charles W. C. Lin SG, Method of making a semiconductor chip assembly.
  110. Lin, Charles W. C., Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive.
  111. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a bumped metal pillar.
  112. Lin,Charles W. C.; Chen,Cheng Chung, Method of making a semiconductor chip assembly with a bumped terminal and a filler.
  113. Lin, Charles W. C.; Chen, Cheng-Chung, Method of making a semiconductor chip assembly with a bumped terminal, a filler and an insulative base.
  114. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a carved bumped terminal.
  115. Wang, Chia-Chung; Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace and a substrate.
  116. Charles W. C. Lin SG, Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.
  117. Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.
  118. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a laterally aligned bumped terminal and filler.
  119. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with a metal containment wall and a solder terminal.
  120. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with a precision-formed metal pillar.
  121. Chiang,Cheng Lien; Lin,Charles W. C., Method of making a semiconductor chip assembly with an embedded metal particle.
  122. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with an interlocked contact terminal.
  123. Lin, Charles W. C., Method of making a semiconductor chip assembly with chip and encapsulant grinding.
  124. Lin, Charles W. C.; Wang, Chia-Chung; Sigmond, David M., Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment.
  125. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding.
  126. Hidetoshi Furukawa JP; Atsushi Noma JP; Tsuyoshi Tanaka JP; Hidetoshi Ishida JP; Daisuke Ueda JP, Method of making a semiconductor device including testing before thinning the semiconductor substrate.
  127. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
  128. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
  129. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.
  130. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.
  131. Charles W. C. Lin SG, Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly.
  132. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture.
  133. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture.
  134. Toshiharu Yanagida JP, Method of making thinned, stackable semiconductor device.
  135. Lin, Charles W. C., Method of manufacturing a multilayer interconnect substrate.
  136. Beatty, John J.; Garcia, Jason A., Method of manufacturing a plurality of electronic assemblies.
  137. Nemoto, Yoshihiko; Fujii, Tomonori; Sunohara, Masahiro; Sato, Tomotoshi, Method of manufacturing a semiconductor device with penetration electrodes that protrude from a rear side of a substrate formed by thinning the substrate.
  138. Chong, Chin Hui; Lee, Choon Kuan, Method of manufacturing an interposer.
  139. Boyle, Adrian A.; Meignan, Oonagh, Methods and systems for laser machining a substrate.
  140. Basker, Veeraraghaven S.; Cotte, John Michael; Deligianni, Hariklia; Knickerbocker, John Ulrich; Kwietniak, Keith T., Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density.
  141. Kirby, Kyle K., Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  142. Kirby, Kyle K., Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  143. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  144. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  145. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  146. Oliver,Steven D.; Kirby,Kyle K.; Hiatt,William M., Methods for forming interconnects in vias and microelectronic workpieces including such interconnects.
  147. Rigg,Sidney B.; Watkins,Charles M.; Kirby,Kyle K.; Benson,Peter A.; Akram,Salman, Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices.
  148. Muthukumar, Sriram; Mancera, Raul; Tomita, Yoshihiro; Hwang, Chi-won, Methods for making multi-chip packaging using an interposer.
  149. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Methods of forming coaxial integrated circuitry interconnect lines.
  150. Akram, Salman; Wark, James M.; Hiatt, William Mark, Methods of forming interconnects and semiconductor structures.
  151. Akram, Salman; Wark, James M.; Hiatt, William M., Methods of forming interconnects in a semiconductor structure.
  152. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.
  153. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.
  154. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filing vias in microelectronic devices.
  155. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filling vias in microelectronic devices.
  156. Kirby, Kyle K.; Akram, Salman; Hembree, David R.; Rigg, Sidney B.; Farnworth, Warren M.; Hiatt, William M., Microelectronic devices and methods for forming interconnects in microelectronic devices.
  157. Kirby, Kyle K.; Akram, Salman; Hembree, David R.; Rigg, Sidney B.; Farnworth, Warren M.; Hiatt, William M., Microelectronic devices and methods for forming interconnects in microelectronic devices.
  158. Parks, Jay S., Microelectronic die including low RC under-layer interconnects.
  159. Parks, Jay S., Microelectronic die including low RC under-layer interconnects.
  160. Clark, Douglas; Oliver, Steven D.; Kirby, Kyle K.; Dando, Ross S., Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces.
  161. Rigg, Sidney B.; Watkins, Charles M.; Kirby, Kyle K.; Benson, Peter A.; Akram, Salman, Microelectronics devices, having vias, and packaged microelectronic devices having vias.
  162. Lee, Teck Kheng; Lim, Andrew Chong Pei, Microfeature workpiece substrates having through-substrate vias, and associated methods of formation.
  163. Hiatt, William M.; Dando, Ross S., Microfeature workpieces and methods for forming interconnects in microfeature workpieces.
  164. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  165. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  166. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  167. Tuttle, Mark E., Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods.
  168. Tuttle, Mark E., Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods.
  169. Muthukumar, Sriram; Mancera, Raul; Tomita, Yoshihiro; Hwang, Chi-won, Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias.
  170. Muthukumar, Sriram; Mancera, Raul; Tomita, Yoshihiro; Hwang, Chi-won, Multi-chip packaging using an interposer with through-vias.
  171. Chang, Hung-Pin; Chiu, Chien-Ming; Wu, Tsang-Jiuh; Shue, Shau-Lin; Yu, Chen-Hua, Multi-layer interconnect structure for stacked dies.
  172. Chang, Hung-Pin; Chiu, Chien-Ming; Wu, Tsang-Jiuh; Shue, Shau-Lin; Yu, Chen-Hua, Multi-layer interconnect structure for stacked dies.
  173. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  174. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  175. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  176. Hayasaka,Nobuo; Okumura,Katsuya; Sasaki,Keiichi; Matsuo,Mie, Multichip semiconductor device, chip therefor and method of formation thereof.
  177. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip VIAS in stacked chips.
  178. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura, Off-chip vias in stacked chips.
  179. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
  180. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
  181. Lin, Chun-Te; Kuo, Tzu-Ying; Chang, Shu-Ming, Package structure of three-dimensional stacking dice and method for manufacturing the same.
  182. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  183. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  184. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  185. Wood Alan G. ; Farnworth Warren M., Process for packaging a semiconductor die using dicing and testing.
  186. Chia Chok J. ; Lim Seng Sooi ; Variot Patrick, Process for using a removeable plating bus layer for high density substrates.
  187. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura, Reconstituted wafer stack packaging with after-applied pad extensions.
  188. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura Wills, Reconstituted wafer stack packaging with after-applied pad extensions.
  189. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.
  190. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.
  191. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.
  192. Akram,Salman; Wark,James M.; Hiatt,William M., Selective nickel plating of aluminum, copper, and tungsten structures.
  193. Takaoka,Yuji, Semiconductor apparatus and method of manufacturing same.
  194. Charles W. C. Lin SG, Semiconductor chip assembly with ball bond connection joint.
  195. Lin, Charles W. C.; Chiang, Cheng-Lien, Semiconductor chip assembly with bumped conductive trace.
  196. Lin, Charles W.C.; Chiang, Cheng-Lien, Semiconductor chip assembly with bumped conductive trace.
  197. Lin,Charles W. C.; Chiang,Cheng Lien, Semiconductor chip assembly with bumped metal pillar.
  198. Charles W. C. Lin SG, Semiconductor chip assembly with bumped molded substrate.
  199. Lin,Charles W. C.; Chen,Cheng Chung, Semiconductor chip assembly with bumped terminal and filler.
  200. Lin, Charles W. C.; Chen, Cheng Chung, Semiconductor chip assembly with bumped terminal, filler and insulative base.
  201. Lin,Charles W. C.; Chiang,Cheng Lien, Semiconductor chip assembly with carved bumped terminal.
  202. Wang, Chia-Chung; Lin, Charles W. C., Semiconductor chip assembly with chip in substrate cavity.
  203. Lin, Charles W. C., Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit.
  204. Chiang,Cheng Lien; Lin,Charles W. C., Semiconductor chip assembly with embedded metal particle.
  205. Leu,Chuen Rong; Lin,Charles W. C., Semiconductor chip assembly with embedded metal pillar.
  206. Leu,Chuen Rong; Lin,Charles W. C., Semiconductor chip assembly with embedded metal pillar.
  207. Lin, Charles W. C., Semiconductor chip assembly with hardened connection joint.
  208. Lin, Charles W. C., Semiconductor chip assembly with interlocked conductive trace.
  209. Lin, Charles W.C., Semiconductor chip assembly with interlocked conductive trace.
  210. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with interlocked contact terminal.
  211. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Semiconductor chip assembly with laterally aligned bumped terminal and filler.
  212. Lin,Charles W. C.; Chen,Cheng Chung, Semiconductor chip assembly with laterally aligned filler and insulative base.
  213. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with metal containment wall and solder terminal.
  214. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with precision-formed metal pillar.
  215. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.
  216. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.
  217. Charles W. C. Lin SG, Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint.
  218. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint.
  219. Lin,Charles W. C., Semiconductor chip assembly with welded metal pillar.
  220. Lin, Charles W. C.; Chen, Cheng-Chung, Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal.
  221. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with welded metal pillar of stacked metal balls.
  222. Lin,Charles W. C., Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond.
  223. Kawano, Masaya; Soejima, Koji; Takahashi, Nobuaki, Semiconductor device.
  224. Kawano, Masaya; Soejima, Koji; Takahashi, Nobuaki, Semiconductor device.
  225. Noma, Takashi; Morita, Yuichi; Yamada, Hiroshi; Okada, Kazuo; Kitagawa, Katsuhiko; Okubo, Noboru; Ishibe, Shinzo; Shinogi, Hiroyuki, Semiconductor device and manufacturing method thereof.
  226. Noma, Takashi; Otsuka, Shigeki; Morita, Yuichi; Okada, Kazuo; Yamada, Hiroshi; Kitagawa, Katsuhiko; Okubo, Noboru; Ishibe, Shinzo; Shinogi, Hiroyuki, Semiconductor device and manufacturing method thereof.
  227. Na, Duk Ju; Chia, Lai Yee; Yong, Chang Beom, Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer.
  228. Na, Duk Ju; Chia, Lai Yee; Yong, Chang Beom, Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer.
  229. Na, Duk Ju; Tan, Calvert; Yong, Chang Beom, Semiconductor device and method of forming through-silicon-via with sacrificial layer.
  230. Kitagawa, Katsuhiko; Shinogi, Hiroyuki; Ishibe, Shinzo; Yamada, Hiroshi, Semiconductor device and method of manufacturing the same.
  231. Shinji Tanabe JP, Semiconductor device and method of manufacturing the same.
  232. Nemoto, Yoshihiko, Semiconductor device manufacturing method and electronic equipment using same.
  233. Nemoto, Yoshihiko, Semiconductor device manufacturing method and electronic equipment using same.
  234. Akram, Salman; Wark, James M.; Hiatt, William M., Semiconductor device structures including nickel plated aluminum, copper, and tungsten structures.
  235. Akram, Salman; Wark, James M.; Hiatt, William Mark, Semiconductor devices comprising nickel- and copper-containing interconnects.
  236. Chong, John; Lee, Seung Bok; MacDonald, Noel; Lewis, Robert; Hunt, Peter, Shaped electrodes for micro-electro-mechanical-system (MEMS) devices to improve actuator performance and methods for fabricating the same.
  237. Ahn, Kie Y.; Forbes, Leonard, Silicon interposer with optical connections.
  238. Kie Y. Ahn ; Leonard Forbes, Silicon interposer with optical connections.
  239. Chong,Chin Hui; Lee,Choon Kuan, Slanted vias for electrical circuits on circuit boards and other substrates.
  240. Avsian, Osher; Grinman, Andrey; Humpston, Giles; Margalit, Moti, Stack packages using reconstituted wafers.
  241. Pohl, Jens; Brunnbauer, Markus; Escher-Poeppel, Irmgard; Meyer, Thorsten, Stackable semiconductor package with encapsulant and electrically conductive feed-through.
  242. Haba, Belgacem; Mohammed, Ilyas, Stacked assembly including plurality of stacked microelectronic elements.
  243. Kriman, Moshe; Avsian, Osher; Haba, Belgacem; Humpston, Giles; Burshtyn, Dmitri, Stacked microelectronic assemblies having vias extending through bond pads.
  244. Ahn Kie Y. ; Forbes Leonard ; Cloud Eugene H., Structure and method for a high performance electronic packaging assembly.
  245. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Structure and method for a high-performance electronic packaging assembly.
  246. Geusic Joseph E. ; Forbes Leonard ; Ahn Kie Y., Structure and method for an electronic assembly.
  247. Joseph E. Geusic ; Leonard Forbes ; Kie Y. Ahn, Structure and method for an electronic assembly.
  248. Uzoh, Cyprian Emeka; Monadgemi, Pezhman; Caskey, Terrence; Ayatollahi, Fatima Lina; Haba, Belgacem; Woychik, Charles G.; Newman, Michael, Structures for heat dissipating interposers.
  249. Halahan, Patrick B., Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity.
  250. Lin, Charles W. C., Support circuit with a tapered through-hole for a semiconductor chip assembly.
  251. Watkins, Charles M.; Hiatt, William M., System and methods for forming apertures in microfeature workpieces.
  252. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  253. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  254. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  255. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  256. Oleg Siniaguine ; Patrick B. Halahan ; Sergey Savastiouk, Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners.
  257. Wu,Weng Jin; Chiou,Wen Chih, Three dimensional integrated circuit and method of making the same.
  258. Pogge,H. Bernhard; Yu,Roy, Three-dimensional device fabrication method.
  259. Lin,Charles W. C.; Chiang,Cheng Lien, Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture.
  260. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Through silicon via structure.
  261. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Through silicon via structure.
  262. Yu, Chen-Hua; Jeng, Shin-Puu; Chiou, Wen-Chih; Tsai, Fang Wen; Tsai, Chen-Yu, Through silicon via structure.
  263. Gong, Shunqiang; Tan, Juan Boon; Liu, Wei, Through via contacts with insulated substrate.
  264. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
  265. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
  266. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
  267. Chauhan, Satyendra Singh, Thru silicon enabled die stacking scheme.
  268. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  269. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  270. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  271. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  272. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  273. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  274. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  275. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  276. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  277. Chen, Ming-Fa; Chiou, Wen-Chih; Shue, Shau-Lin, Wafer backside interconnect structure connected to TSVs.
  278. Chen, Ming-Fa; Chiou, Wen-Chih; Shue, Shau-Lin, Wafer backside interconnect structure connected to TSVs.
  279. Chen, Ming-Fa; Chiou, Wen-Chih; Shue, Shau-Lin, Wafer backside interconnect structure connected to TSVs.
  280. Chen, Ming-Fa; Chiou, Wen-Chih; Shue, Shau-Lin, Wafer backside interconnect structure connected to TSVs.
  281. Haba, Belgacem; Mohammed, Ilyas; Mirkarimi, Laura; Kriman, Moshe, Wafer level edge stacking.
  282. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
  283. Chung, Hyun Soo; Lee, Ho Jin; Jang, Dong Hyun; Lee, Dong Ho, Wafer level package having a stress relief spacer and manufacturing method thereof.
  284. Chung, Hyun-Soo; Lee, Ho-Jin; Jang, Dong-Hyun; Lee, Dong-Ho, Wafer level package having a stress relief spacer and manufacturing method thereof.
  285. Chung, Hyun-Soo; Lee, Ho-Jin; Jang, Dong-Hyun; Lee, Dong-Ho, Wafer level package having a stress relief spacer and manufacturing method thereof.
  286. Chung, Hyun-Soo; Lee, Ho-Jin; Jang, Dong-Hyun; Lee, Dong-Ho, Wafer level package having a stress relief spacer and manufacturing method thereof.
  287. Chung, Hyun-Soo; Lee, Ho-Jin; Jang, Dong-Hyun; Lee, Dong-Ho, Wafer level package having a stress relief spacer and manufacturing method thereof.
  288. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode and wafer-level light emitting diode package.
  289. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode package and method of fabricating the same.
  290. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode package and method of fabricating the same.
  291. Cho Ching-Fai ; Maiershofer Helmut Carl ; Shin Do Bum ; Quil Avery Yee, Wide frequency band transition between via RF transmission lines and planar transmission lines.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로