$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0544540 (1995-10-18)
우선권정보 JP-0260449 (1994-10-25)
발명자 / 주소
  • Ohno Yasuhiro (Tokyo JPX) Miyata Manabu (Tokyo JPX)
출원인 / 주소
  • Oki Electric Industry Co., Ltd. (Tokyo JPX 03)
인용정보 피인용 횟수 : 94  인용 특허 : 0

초록

In a semiconductor memory, a plurality of semiconductor memory modules are connected through a common clock signal line and one or more other signal lines to an accessing circuit. The accessing circuit has a timing information storage unit for storing predetermined access timing information associat

대표청구항

A semiconductor memory comprising: a plurality of semiconductor memory modules; a common clock signal line; at least one other common signal line; and an accessing circuit, connected through said common clock signal line and said at least one other common signal line to said plurality of semiconduct

이 특허를 인용한 특허 (94)

  1. Dean Gans ; Eric J. Stave ; Joseph Thomas Pawlowski, Adjustable I/O timing from externally applied voltage.
  2. Patrick J. Mullarkey, Apparatus for adjusting delay of a clock signal relative to a data signal.
  3. Tojima, Masayoshi; Nakajima, Hiromasa; Oohashi, Masahiro; Kohashi, Yasuo, Clock phase adjustment method, and integrated circuit and design method therefor.
  4. Tojima, Masayoshi; Nakajima, Hiromasa; Oohashi, Masahiro; Kohashi, Yasuo, Clock phase adjustment method, integrated circuit, and method for designing the integrated circuit.
  5. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Clocked memory system with termination component.
  6. Patrick J. Mullarkey, Computer system having memory device with adjustable data clocking.
  7. Mullarkey, Patrick J., Computer system having memory device with adjustable data clocking using pass gates.
  8. Lin, Chih-Hung; Ko, Tsung-Hsiu; Su, Wei-Li, Data sampling and data encryption/decryption method and electronic device utilizing the methods.
  9. Millar Bruce,CAX, De-skewing data signals in a memory system.
  10. Manning Troy A., Delay-locked loop with binary-coupled capacitor.
  11. Manning Troy A., Delay-locked loop with binary-coupled capacitor.
  12. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
  13. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
  14. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
  15. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.
  16. Chris G. Martin, Digital delay, digital phase shifter.
  17. Bonella, Randy M.; Halbert, John B., Digital system of adjusting delays on circuit boards.
  18. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
  19. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
  20. Lee,Terry R.; Jeddeloh,Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.
  21. Nobutsugu Odani JP, Electric device with flash memory built-in.
  22. Rao, Hari M.; Kim, Jung Pill; Kang, Seung H.; Zhu, Xiaochun; Kim, Tae Hyun; Lee, Kangho; Li, Xia; Hsu, Wah Nam; Hao, Wuyang; Suh, Jungwon; Yu, Nicholas K.; Nowak, Matthew Michael; Millendorf, Steven M.; Ashkenazi, Asaf, Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction.
  23. Barth, Richard M.; Ware, Frederick A.; Stark, Donald C.; Hampel, Craig E.; Davis, Paul G.; Abhyankar, Abhijit M.; Gasbarro, James A.; Nguyen, David, Interface for a semiconductor memory device and method for controlling the interface.
  24. Iwata,Yoshihisa; Nakajima,Kentaro, Magnetic random access memory.
  25. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory component that samples command/address signals in response to both edges of a clock signal.
  26. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory component with terminated and unterminated signaling inputs.
  27. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory controller.
  28. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory controller.
  29. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory controller.
  30. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory controller.
  31. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory controller device having timing offset capability.
  32. Barth, Richard M.; Ware, Frederick A.; Stark, Donald C.; Hampel, Craig E.; Davis, Paul G.; Abhyankar, Abhijit M.; Gasbarro, James A.; Nguyen, David, Memory controller for controlling write signaling.
  33. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory controller that enforces strobe-to-strobe timing offset.
  34. Ware, Frederick A., Memory controller with clock-to-strobe skew compensation.
  35. Ware, Frederick A., Memory controller with clock-to-strobe skew compensation.
  36. Ware, Frederick A., Memory controller with clock-to-strobe skew compensation.
  37. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory controller with selective data transmission delay.
  38. Jung,Tae sung; Song,Won ki, Memory device controls delay time of data input buffer in response to delay control information based on a position of a memory device received from memory controller.
  39. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory module.
  40. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory module.
  41. Park Young Gi,KRX ; Kim Ji Bum,KRX, Memory module having module control circuit.
  42. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory module with termination component.
  43. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Memory module with termination component.
  44. Osaka,Hideki; Komatsu,Toyohiko; Horiguchi,Masashi; Hatano,Susumu; Ito,Kazuya, Memory system.
  45. Wiggers Hans A., Memory system and device.
  46. Keeth, Brent, Memory system with dynamic timing correction.
  47. Deneroff Martin M. ; Sarocky Kenneth M. ; McCall David Leo ; McCracken David Edward, Memory system with switching for data isolation.
  48. Barth, Richard M.; Ware, Frederick A.; Stark, Donald C.; Hampel, Craig E.; Davis, Paul G.; Abhyankar, Abhijit M.; Gasbarre, James A.; Nguyen, David, Memory write signaling and methods thereof.
  49. Gans Dean ; Wilford John R. ; Pawlowski Joseph T., Method and apparatus for adjusting control signal timing in a memory device.
  50. Gans Dean ; Wilford John R. ; Pawlowski Joseph T., Method and apparatus for adjusting control signal timing in a memory device.
  51. Mullarkey Patrick J., Method and apparatus for adjusting data timing by delaying clock signal.
  52. Keeth, Brent; Manning, Troy A., Method and apparatus for adjusting the timing of signals over fine and coarse ranges.
  53. Brent Keeth ; Terry R. Lee ; Kevin Ryan ; Troy A. Manning, Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
  54. Keeth, Brent; Lee, Terry R.; Ryan, Kevin; Manning, Troy A., Method and apparatus for bit-to-bit timing correction of a high speed memory bus.
  55. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  56. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  57. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  58. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  59. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.
  60. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
  61. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.
  62. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
  63. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
  64. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.
  65. Harrison,Ronnie M., Method and apparatus for generating a sequence of clock signals.
  66. Troy A. Manning, Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal.
  67. Manning, Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  68. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  69. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  70. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  71. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.
  72. Brent Keeth, Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same.
  73. Barth, Richard M.; Ware, Frederick A.; Stark, Donald C.; Hampel, Craig E.; Davis, Paul G.; Abhyankar, Abhijit M.; Gasborro, James A.; Nguyen, David, Method and apparatus for indicating mask information.
  74. Manning Troy A., Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device.
  75. Troy A. Manning, Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same.
  76. Ware, Frederick A.; Tsern, Ely K.; Perego, Richard E.; Hampel, Craig E., Method and apparatus for signaling between devices of a memory system.
  77. Jakobs, Andreas; Plaettner, Eckehard, Method and circuit arrangements for adjusting signal propagation times in a memory system.
  78. Hashimoto, Michitaka, Method and memory controller.
  79. Johnson, Brian; Harrison, Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
  80. Johnson,Brian; Harrison,Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.
  81. Manning, Troy A., Method for generating expect data from a captured bit pattern, and memory device using same.
  82. Hwang, Kyo-Jong; Kim, Young-Keun; Kim, Yoon-Soo, Multimedia modular card, device for operating the same, and integrated multimedia system.
  83. Rao, Hari M.; Kim, Jung Pil; Kang, Seung H.; Zhu, Xiaochun; Kim, Tae Hyun; Lee, Kangho; Li, Xia; Hsu, Wah Nam; Hao, Wuyang; Suh, Jungwon; Yu, Nicholas K.; Nowak, Matthew Michael; Millendorf, Steven M.; Ashkenazi, Asaf, Non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction.
  84. Kamibeppu, Osamu, Non-volatile semiconductor memory device.
  85. Goto, Hiroyuki; Shiota, Shigemasa; Tamura, Takayuki; Shibuya, Hirofumi; Nakamura, Yasuhiro, Nonvolatile memory system.
  86. Gillingham, Peter Bruce, Read/write timing for maximum utilization of bi-directional read/write bus.
  87. Fagan, John L.; Bossard, Mark, Selectable delay pulse generator.
  88. Choi Hoon,KRX ; Kim Sei-jin,KRX ; Maesako Taketo,JPX, Semiconductor memory device and method for improving the transmission data rate of a data input and output bus and memory module.
  89. Matsubara Yasushi,JPX ; Ishioka Hiroshi,JPX, Synchronous DRAM having a high data transfer rate.
  90. Mullarkey Patrick J., Synchronous memory device having an adjustable data clocking circuit.
  91. Tietjen Donald L. ; Biggs Terry L., Synchronous memory interface.
  92. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
  93. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
  94. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로