[특허]Multiprocessor system for locally managing address translation table

Multiprocessor system for locally managing address translation table 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-012/10
출원번호	US-0497447 (1995-06-30)
우선권정보	JP-0149440 (1994-06-30)
발명자 / 주소	Yamazaki Takeshi (Tokyo JPX)
출원인 / 주소	NEC Corporation (Tokyo JPX 03)
인용정보	피인용 횟수 : 38 인용 특허 : 0

초록 ▼

An address translation technique used in a multiprocessor system is disclosed. In a multiprocessor system for connecting a plurality of clusters with each other via a network, each of these clusters is arranged by comprising a plurality of processors; a cluster translator for translating a cluster number; a cluster translation table for storing therein a correspondence relationship between a logical cluster number and a physical cluster number; an address translator for translating an address; and an address translation table for storing therein a correspondence relationship between a logical address and a physical address. The address translation table stores only the data corresponding to a memory employed in the cluster. Accordingly, a total storage capacity of the address translation tables is reduced, and an updating operation of the address translation tables is simplified. Furthermore, the address translation table is exclusively identified based on a local job number and the cluster number, so that operation to update the address translation table is simplified.

대표청구항 ▼

A multiprocessor system comprising a plurality of clusters each having a memory and at least one processor, and a network for connecting said plural clusters with each other, wherein: a first cluster includes cluster translating means for translating a virtual address corresponding to a first memory access request issued from a processor in the first cluster into an intermediate address, and for sending a second memory access request, based on the intermediate address, via said network to a second cluster when the intermediate address corresponds to said second cluster; and said second cluster includes address translating means for producing a physical address from the intermediate address corresponding to said second memory access request issued from said first cluster, thereby accessing to a memory in the second cluster designated by said produced physical address, and wherein: said virtual address includes a source local job number allocated to a job executed by said processor in said first cluster, a destination logical cluster number, and a logical address; said intermediate address includes a destination local job number, a destination physical cluster number, and the logical address; said cluster translating means generates the destination local job number and the destination physical cluster number from the source local job number and the destination logical cluster number, said first cluster sending the second memory access request to said second cluster when a cluster designated by the destination physical cluster number corresponds to said second cluster; said network transfers the second memory access request issued from said first cluster to said second cluster in accordance with the destination physical cluster number of said second cluster; and said address translating means produces a physical address from both of the destination local job number in said second cluster and the logical address within said second cluster, thereby accessing to said memory in the second cluster designated by said produced physical address.

이 특허를 인용한 특허 (38)

Jander Mark J. ; Solomon Richard L., Apparatus and method for address translation in bus bridge devices.
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Jander Mark J. ; Solomon Richard L., Apparatus and method for address translation in bus bridge devices.
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Vishin Sanjay ; Aybay Gunes, Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces.
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Medina, Eitan; Rozenzveig, Rami; Shemla, David, Bit clearing mechanism for an empty list.
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Medina, Eitan; Rozenzveig, Rami; Shemla, David, Bit clearing mechanism for an empty list.
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Medina,Eitan; Rozenzveig,Rami; Shemla,David, Bit clearing mechanism for an empty list.
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Shemla,David; Waldman,Eyal; Solt,Yosi, Bus protocol.
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Beckhoff, Hans; Buttner, Holger, Data transmission method, serial bus system, and switch-on unit for a passive station.
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Faanes,Gregory J.; Scott,Steven L.; Lundberg,Eric P.; Moore, Jr.,William T.; Johnson,Timothy J., Decoupled scalar/vector computer architecture system and method.
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Scott, Steven L.; Faanes, Gregory J., Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system.
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Kohn,James R., Indirectly addressed vector load-operate-store method and apparatus.
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Scott, Steven L., Latency tolerant distributed shared memory multiprocessor computer.
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Blackmore, Robert S.; Kandadai, Radha R.; Kim, Chulho; Mendel, Gili; Shah, Gautam H., Mapping a logical address to a plurality on non-logical addresses.
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Pautsch, Gregory W.; Pautsch, Adam, Method and apparatus for cooling electronic components.
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Kohn, James R., Method and apparatus for indirectly addressed vector load-add-store across multi-processors.
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Kohn,James R., Method and apparatus for indirectly addressed vector load-add-store across multi-processors.
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Franklin, Jeffrey B., Method and system for hosting multiple, customized computing clusters.
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Novaes,Marcos N.; Laib,Gregory D.; Goering,Ronald T.; Lucash,Jeffrey S.; Badovinatz,Peter R.; Schmidt,Michael A., Method, system and program products for managing a clustered computing environment.
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Ikeda Masayuki,JPX ; Nagasawa Shigeru,JPX ; Ueno Haruhiko,JPX ; Shinjo Naoki,JPX ; Utsumi Teruo,JPX ; Kobayakawa Kazushige,JPX ; Sueyasu Naoki,JPX ; Ishizaka Kenichi,JPX ; Dewa Masami,JPX ; Takamura , Multiprocessor system and parallel processing method for processing data transferred between processors.
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Nesheim William A. ; Guzovskiy Aleksandr, Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of.
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Scott,Steven L.; Faanes,Gregory J.; Stephenson,Brick; Moore, Jr.,William T.; Kohn,James R., Multistream processing memory-and barrier-synchronization method and apparatus.
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Scott,Steven L.; Dickson,Chris; Reinhardt,Steve, Node translation and protection in a clustered multiprocessor system.
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Scott, Steven L.; Faanes, Gregory J.; Stephenson, Brick; Moore, Jr., William T.; Kohn, James R., Relaxed memory consistency model.
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Scott, Steven L.; Dickson, Chris; Fromm, Eric C.; Anderson, Michael L., Remote address translation in a multiprocessor system.
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Scott, Steven L., Remote translation mechanism for a multi-node system.
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Sheets, Kitrick; Hastings, Andrew B., Remote translation mechanism for a multinode system.
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Klausler, Peter M., Scheduling synchronization of programs running as streams on multiple processors.
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Sheets,Kitrick; Williams,Josh; Gettler,Jonathan; Piatz,Steve; Hastings,Andrew B.; Hill,Peter; Bravatto,James G.; Kohn,James R.; Titus,Greg, Scheduling synchronization of programs running as streams on multiple processors.
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Sheets, Kitrick, Sharing memory within an application using scalable hardware resources.
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Shemla David,ILX ; Willenz Avigdor,ILX, Switching ethernet controller.
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Shemla, David; Willenz, Avigdor, Switching ethernet controller.
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Shemla, David; Willenz, Avigdor, Switching ethernet controller.
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Shemla, David; Willenz, Avigdor, Switching ethernet controller.
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Shemla,David; Willenz,Avigdor, Switching ethernet controller.
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Faanes, Gregory J.; Lundberg, Eric P.; Scott, Steven L.; Baird, Robert J., System and method for processing memory instructions using a forced order queue.
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Beukema, Bruce Leroy; Bronson, Timothy Carl; Fuhs, Ronald Edward; Gilda, Glenn David; Bybell, Anthony J; Jackowski, Stefan Peter; Verdoorn, Jr., William Garrett; Williams, Phillip G, System and method for supporting access to multiple I/O hub nodes in a host bridge.
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Uceda-Sosa, Rosario A.; Marthi, Kailash N.; Champagne, Steven R., System and program products for efficiently locking resources of a global data repository.
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Franklin, Jeffrey B., System for hosting customized computing clusters.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Multiprocessor system for locally managing address translation table 원문보기

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Multiprocessor system for locally managing address translation table 원문보기

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