초록 ▼

A structure for reducing the OFF current of an active matrix display. In the active matrix display, plural TFTs are connected in series with each one pixel electrode. Of these TFTs connected in series, at least one TFT excluding the TFTs located at opposite ends is maintained in conduction. Alternat

A structure for reducing the OFF current of an active matrix display. In the active matrix display, plural TFTs are connected in series with each one pixel electrode. Of these TFTs connected in series, at least one TFT excluding the TFTs located at opposite ends is maintained in conduction. Alternatively, at least one capacitor is connected between the junction of the drain and source of each TFT connected in series and an AC grounded point. Thus, the amount of electric charge released from auxiliary capacitors during cutoff of the TFTs is reduced.

대표청구항 ▼

An active matrix display comprising: pixel electrodes arranged in rows and columns; semiconductor film islands, each one of said islands being provided for each one of said pixel electrodes, said islands having N- or P-type regions; and at least three gate electrodes provided on each one of said sem

An active matrix display comprising: pixel electrodes arranged in rows and columns; semiconductor film islands, each one of said islands being provided for each one of said pixel electrodes, said islands having N- or P-type regions; and at least three gate electrodes provided on each one of said semiconductor film islands and coated with an anodic oxide film to provide at least three thin film transistors on said each one of said semiconductor film islands, said three thin film transistors having three gate electrodes respectively, said three thin film transistors being connected in series with each other with gates of two of said three thin film transistors being connected with a gate signal line, and a gate of the other of said three thin film transistors being connected with a capacitor line, wherein one of source and drain of the other of said three thin film transistors is connected with one of source and drain of one of said two of said three thin film transistors, and the other of the source and drain of the other of said three thin film transistors is connected with one of source and drain of the other of said two of said three thin film transistors, and the other of the source and drain of said one of said two of said three thin film transistors is connected with an image signal line, and the other of the source and drain of the other of said two of said three thin film transistors is connected with the corresponding one of said pixel electrodes, and wherein said gate connected with said capacitor line is applied with a signal which activates said gate connected with said capacitor line at least for a major portion of a time during which a select signal is not applied to the gate signal line.