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Disposable posts for self-aligned non-enclosed contacts 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/28
출원번호 US-0581061 (1995-12-29)
발명자 / 주소
  • Cleeves James M. (Redwood City CA)
출원인 / 주소
  • Cypress Semiconductor Corporation (CA 02)
인용정보 피인용 횟수 : 44  인용 특허 : 6

초록

A disposable post process for contact openings to interconnect material of reduced geometry and no enlarged landing pads is disclosed. A layer of material is formed over interconnect regions on a semiconductor wafer and subsequently patterned into posts which define the location and shape of opening

대표청구항

A method for forming an opening over an interconnect on a semiconductor wafer, comprising the steps of: (a) forming an interconnect without an enlarged landing pad; (b) forming a first layer having a first material over the interconnect; (c) patterning the layer of first material to form a post over

이 특허에 인용된 특허 (6)

  1. Dixit Pankaj (Sunnyvale CA) Sliwa Jack (Los Altos Hills CA) Klein Richard K. (Mountain View CA) Sander Craig S. (Mountain View CA) Farnaam Mohammad (Santa Clara CA), Contact plug and interconnect employing a barrier lining and a backfilled conductor material.
  2. Fujita Tsutomu (Hirakata JPX) Kakiuchi Takao (Takarazuka JPX) Yamamoto Hiroshi (Neyagawa JPX) Tanimura Shoichi (Hirakata JPX), Method for filling contact hole.
  3. Park Sang H. (Bubaleub ; Ichonkun KRX), Method for forming metal interconnection of semiconductor device.
  4. Pintchovski Faivel (Austin TX) Tobin Philip J. (Austin TX), Method for making a w/tin contact.
  5. Bornstein Johnathan G. (Cupertino CA) Caldwell Roger (Milpitas CA), Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an asso.
  6. Onishi Shigeo (Nara JPX) Yamadai Tsutomu (Nara JPX) Ishihara Kazuya (Tenri JPX), Process for fabricating a semiconductor device including a tungsten silicide adhesive layer.

이 특허를 인용한 특허 (44)

  1. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  2. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
  3. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.
  4. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.
  5. Weber Heribert,DEX, Conductor path contacting arrangement and method.
  6. Yu Chia-Chieh,TWX, Damascene process.
  7. Sung-Kwon Lee KR, Device formation method for preventing pattern shift caused by glass layer reflow.
  8. Tobben Dirk, Dual damascene process for metal layers and organic intermetal layers.
  9. Shields, Jeffrey A.; Rangarajan, Bharath, Dual width contact for charge gain reduction.
  10. Chao Li-Chih,TWX ; Tsai Chia-Shiung,TWX ; Fu Chu-Yun,TWX ; Liaw Jhon-Jhy,TWX, High selectivity etching stop layer for damascene process.
  11. Yin, Zhiping; Jost, Mark E., Interconnect structures with interlayer dielectric.
  12. Dass M. Lawrence A. ; Karklin Kenneth D. ; Seshan Krishna ; Roggel Amir, KLXX technology with integrated passivation process, probe geometry and probing process.
  13. Lee Young Hoon ; Zhang Ying, Method for forming vias and trenches in an insulation layer for a dual-damascene multilevel interconnection structure.
  14. Chen Shiaw-Rong,CNX ; Lu Horng-Bor,CNX ; Lin Jenn-Tarng,CNX, Method for treating via sidewalls with hydrogen plasma.
  15. Gonzalez, Fernando; Lowrey, Tyler A.; Doan, Trung Tri; Turi, Raymond A.; Wolstenholme, Graham R., Method of making vertical diode structures.
  16. Gonzalez, Fernando; Lowrey, Tyler A.; Doan, Trung Tri; Turi, Raymond A.; Wolstenholme, Graham R., Method of making vertical diode structures.
  17. Gonzalez, Fernando; Lowrey, Tyler A.; Doan, Trung Tri; Turi, Raymond A.; Wolstenholme, Graham R., Method of making vertical diode structures.
  18. Oh,Sang Hun, Methods for forming a metal line in a semiconductor manufacturing process.
  19. Wang Fei ; Ngo Minh Van ; Chan Darin A. ; Foote David K. ; En William G., Methods for preventing deleterious punch-through during local interconnect formation.
  20. Givens, John H.; Jost, Mark E., Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  21. Yu Jengyi, Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit.
  22. Yu, Jengyi, Methods of filling constrained spaces with insulating materials and/or of forming contact holes and/or contacts in an integrated circuit.
  23. Cleeves, James M., Post vertical interconnects formed with silicide etch stop and method of making.
  24. Cleeves,James M., Post vertical interconnects formed with silicide etch stop and method of making.
  25. Hung-Sheng Chen ; Unsoon Kim ; Yu Sun ; Chi Chang ; Mark Ramsbey ; Mark Randolph ; Tatsuya Kajita ; Angela Hui ; Fei Wang ; Mark Chang, Process for fabricating an integrated circuit with a self-aligned contact.
  26. Boyd Diane C. ; Furukawa Toshiharu ; Holmes Steven J. ; Ma William H. ; Rabidoux Paul A. ; Horak David V., Resist image reversal by means of spun-on-glass.
  27. Harada Akihiko,JPX ; Higashitani Keiichi,JPX, Semiconductor device and method of manufacturing semiconductor device.
  28. Gonzalez, Fernando; Lowrey, Tyler A.; Doan, Trung T.; Turi, Raymond A.; Wolstenholme, Graham R., Semiconductor structures including vertical diode structures and methods for making the same.
  29. Gonzalez, Fernando; Lowrey, Tyler A.; Doan, Trung Tri; Turi, Raymond A.; Wolstenholme, Graham R., Semiconductor structures including vertical diode structures and methods of making the same.
  30. Narayan Chandrasekhar ; Dinkel Bettina, Soft passivation layer in semiconductor fabrication.
  31. Jeffrey A. Shields ; Bharath Rangarajan, Spacer narrowed, dual width contact for charge gain reduction.
  32. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  33. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  34. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  35. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  36. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  37. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  39. Givens, John H.; Jost, Mark E., Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  40. Givens, John H.; Jost, Mark E., Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  41. John H. Givens ; Mark E. Jost, Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  42. Gonzalez,Fernando; Lowrey,Tyler A.; Doan,Trung Tri; Turi,Raymond A.; Wolstenholme,Graham R., Vertical diode structures.
  43. Gonzalez,Fernando; Lowrey,Tyler A.; Doan,Trung Tri; Turi,Raymond A.; Wolstenholme,Graham R., Vertical diode structures.
  44. Gonzalez,Fernando; Lowrey,Tyler A.; Doan,Trung Tri; Turi,Raymond A.; Wolstenholme,Graham R., Wafer with vertical diode structures.
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