IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0630708
(1996-04-08)
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발명자
/ 주소 |
- Adrian Ng Choon Seng (Singapore SGX)
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출원인 / 주소 |
- Chartered Semiconductor Manufacturing Pte Ltd. (Singapore SGX 03)
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인용정보 |
피인용 횟수 :
23 인용 특허 :
0 |
초록
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A process for creating narrow, metal via structures, used to connect metallization levels, has been developed. The process features initially forming a narrow, metal via structure, and then an underlying interconnect metallization structure, from a single, composite metallization layer. The composit
A process for creating narrow, metal via structures, used to connect metallization levels, has been developed. The process features initially forming a narrow, metal via structure, and then an underlying interconnect metallization structure, from a single, composite metallization layer. The composite metallization layer is composed of conductive layers, with a specific layer used as an etch stop, allowing creation of a narrow metal via structure, from the top layer of the composite metallization layer, without disturbing the bottom layers. The bottom layers of the composite metallization layer are then patterned to create the underlying interconnect metallization structure.
대표청구항
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A method for fabricating a MOSFET device structure, on a semiconductor substrate, using a metal via structure, formed from a composite metallization layer, to provide electrical contact between an underlying interconnect metallization structure, also formed from said composite metallization layer, a
A method for fabricating a MOSFET device structure, on a semiconductor substrate, using a metal via structure, formed from a composite metallization layer, to provide electrical contact between an underlying interconnect metallization structure, also formed from said composite metallization layer, and an overlying interconnect metallization structure, comprising the steps of: providing active device regions in said MOSFET device structure, on said semiconductor substrate; depositing an insulator layer on said semiconductor substrate, including depositing on said active device regions, of said MOSFET device structure; opening a contact hole in said insulator layer, to expose top surface of said active device regions, in said MOSFET device structure; depositing a tungsten layer on top surface of said insulator layer, completely filling said contact hole; removing said tungsten layer from top surface of said insulator layer, forming a tungsten plug in said contact hole; surface cleaning of said tungsten plug; depositing a first titanium nitride barrier layer, on top surface of said insulator layer, and on exposed top surface of said tungsten plug; depositing an underlying, aluminum based metal layer, on said first titanium nitride layer; depositing a first titanium-tungsten barrier layer on said underlying, aluminum based metal layer; depositing an overlying, aluminum based metal layer, on said first titanium-tungsten barrier layer; forming a first photoresist shape on said overlying, aluminum based metal layer; etching of said overlying, aluminum based metal layer, in regions not covered by said first photoresist shape, with etch stopping at said first titanium-tungsten barrier layer, to create said metal via structure, on said first titanium-tungsten barrier layer; removing said first photoresist shape; forming a second photoresist shape on said first titanium-tungsten barrier layer, completely covering said metal via structure; etching of said first titanium-tungsten barrier layer, of said underlying, aluminum based metal layer, and of said first titanium nitride layer, in regions not covered by said second photoresist shape, to create an underlying, composite interconnect metallization structure, underlying said metal via structure, while contacting underlying said tungsten plug; removing said second photoresist shape; depositing a first silicon oxide layer on said metal via structure, on said underlying, composite interconnect metallization structure, and on top surface of said insulator layer, not covered by said underlying, composite interconnect metallization structure; applying a spin on glass layer on said first silicon oxide layer, partially filling spaces between said metal via structure, and between said underlying, composite interconnect metallization structure; heat treating of said spin on glass layer; curing of said spin on glass layer; depositing a second silicon oxide layer on said spin on glass layer, completely filling spaces between said metal via structure, and between said underlying, composite interconnect metallization structure; chemical mechanical polishing to expose top surface of said metal via structure, and to planarize top surface of said first silicon oxide layer, top surface of said spin on glass layer, and top surface of said second silicon oxide layer; depositing a second titanium-tungsten barrier layer on exposed top surface of said metal via structure, and on top surface of said first silicon oxide layer, on top surface of said spin on glass layer, and on top surface of said second silicon oxide layer; depositing a second level, aluminum based layer, on said second titanium-tungsten barrier layer; forming a third photoresist shape on said second level, aluminum based layer; etching of said second level, aluminum based layer, and of said second titanium-tungsten barrier layer, in regions not covered by said third photoresist shape, to create an overlying, composite interconnect metallization structure, contacting underlying, said metal via structure; and removing said third photoresist shape.
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