이 특허를 인용한 특허 (68)

1. Gealy, Dan; Weimer, Ronald A., Ampoules for producing a reaction gas and systems for depositing materials onto microfeature workpieces in reaction chambers.

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2. Carpenter,Craig M.; Mardian,Allen P.; Dando,Ross S.; Tschepen,Kimberly R.; Derderian,Garo J., Apparatus and method for depositing materials onto microelectronic workpieces.

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3. Mardian, Allen P.; Rodriguez, Santiago R., Apparatus and methods for manufacturing microfeatures on workpieces using plasma vapor processes.

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4. Derderian,Garo J., Apparatus and methods for plasma vapor deposition processes.

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5. Carpenter,Craig M.; Dando,Ross S.; Mardian,Allen P., Apparatus for controlling gas pulsing in processes for depositing materials onto micro-device workpieces.

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6. Lee William Wei-Yen, Borderless contacts for dual-damascene interconnect process.

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7. Jigish D. Trivedi ; Ravi Iyer, Conductive structure in an integrated circuit.

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8. Trivedi, Jigish D.; Iyer, Ravi, Conductive structure in an integrated circuit.

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9. Charles H. Dennison, Contact openings, electrical connections and interconnections for integrated circuitry.

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10. Stamper Anthony K. ; McGahay Vincent J., Damascene etchback for low .epsilon. dielectric.

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11. Tsai Chao-Chieh,TWX ; Ho Chin-Hsiung ; Sun Yuan-Chen, Dual damascene interconnect process with borderless contact.

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12. Lytle,Steven A., Dual damascene process with no passing metal features.

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13. Li,Ming Michael, Formation of micro rough polysurface for low sheet resistant salicided sub-quarter micron polylines.

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14. Dennison,Charles H., Integrated circuitry.

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15. Ma,Gordon; Ahrens,Carsten, LDMOS transistor.

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16. Ma,Gordon; Ahrens,Carsten, LDMOS transistor.

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17. Iggulden, Roy C.; Shafer, Padraic; Robl, Werner; Wong, Kwong Hon, Liner with poor step coverage to improve contact resistance in W contacts.

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18. Erik S. Jeng TW; Bi-Ling Chen TW; Chien-Sheng Hsieh TW, Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections.

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19. Jeng Erik S.,TWX ; Chen Bi-Ling,TWX ; Hsieh Chien-Sheng,TWX, Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections.

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20. Fujiwara,Tsuyoshi; Asaka,Katsuyuki; Nariyoshi,Yasuhiro; Hoshino,Yoshinori; Oomori,Kazutoshi, Method for manufacturing semiconductor integrated circuit device.

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21. Trivedi, Jigish D., Method of fabricating a stacked local interconnect structure.

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22. Trivedi,Jigish D., Method of fabricating stacked local interconnect structure.

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23. Chi Min-Hwa,TWX, Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise.

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24. Choe Jeong-Dong,KRX, Method of forming a contact in semiconductor device.

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25. Ngo Minh Van ; Chan Simon S. ; Pangrle Suzette K. ; Huertas Robert A., Method of reducing metal voidings in 0.25 .mu.m AL interconnect.

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26. Zheng,Lingyi A.; Doan,Trung T.; Breiner,Lyle D.; Ping,Er Xuan; Beaman,Kevin L.; Weimer,Ronald A.; Kubista,David J.; Basceri,Cem, Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature workpieces.

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27. Beaman,Kevin L.; Weimer,Ronald A.; Breiner,Lyle D.; Ping,Er Xuan; Doan,Trung T.; Basceri,Cem; Kubista,David J.; Zheng,Lingyi A., Methods and apparatus for processing microfeature workpieces; methods for conditioning ALD reaction chambers.

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28. Beaman, Kevin L.; Doan, Trung T.; Breiner, Lyle D.; Weimer, Ronald A.; Ping, Er-Xuan; Kubista, David J.; Basceri, Cem; Zheng, Lingyi A., Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition.

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29. Beaman, Kevin L.; Doan, Trung T.; Breiner, Lyle D.; Weimer, Ronald A.; Ping, Er-Xuan; Kubista, David J.; Basceri, Cem; Zheng, Lingyi A., Methods and systems for controlling temperature during microfeature workpiece processing, E.G., CVD deposition.

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30. Beaman,Kevin L.; Doan,Trung T.; Breiner,Lyle D.; Weimer,Ronald A.; Ping,Er Xuan; Kubista,David J.; Basceri,Cem; Zheng,Lingyi A., Methods and systems for controlling temperature during microfeature workpiece processing, e.g., CVD deposition.

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31. Carpenter,Craig M.; Dynka,Danny, Methods for controlling mass flow rates and pressures in passageways coupled to reaction chambers and systems for depositing material onto microfeature workpieces in reaction chambers.

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32. Dando, Ross S.; Gealy, Dan, Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces.

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33. Dando, Ross S.; Gealy, Dan, Methods for depositing material onto microfeature workpieces in reaction chambers and systems for depositing materials onto microfeature workpieces.

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34. Zheng, Lingyi A.; Doan, Trung T.; Breiner, Lyle D.; Ping, Er-Xuan; Beaman, Kevin L.; Weimer, Ronald A.; Basceri, Cem; Kubista, David J., Methods for forming small-scale capacitor structures.

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35. Zheng,Lingyi A.; Doan,Trung T.; Breiner,Lyle D.; Ping,Er Xuan; Weimer,Ronald A.; Kubista,David J.; Beaman,Kevin L.; Basceri,Cem, Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces.

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36. Basceri,Cem; Doan,Trung T.; Weimer,Ronald A.; Beaman,Kevin L.; Breiner,Lyle D.; Zheng,Lingyi A.; Ping,Er Xuan; Sarigiannis,Demetrius; Kubista,David J., Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces.

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37. Basceri,Cem; Doan,Trung T.; Weimer,Ronald A.; Beaman,Kevin L.; Breiner,Lyle D.; Zheng,Lingyi A.; Ping,Er Xuan; Sarigiannis,Demetrius; Kubista,David J., Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces.

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38. Goebel, Thomas; Kaltalioglu, Erdem; Naujok, Markus, Passivated copper chip pads.

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39. Goebel, Thomas; Kaltalioglu, Erdem; Naujok, Markus, Passivated copper chip pads.

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40. Findley Paul Raj ; Smith Morgan, Patterned filled layers for integrated circuit manufacturing.

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41. Lin Yung-Fa,TWX, Process for creating vias using pillar technology.

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42. Dando, Ross S., Reactors with isolated gas connectors and methods for depositing materials onto micro-device workpieces.

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43. Miller, Matthew W.; Basceri, Cem, Reactors, systems and methods for depositing thin films onto microfeature workpieces.

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44. Ronald Kakoschke DE; Regina Stokan DE, Semiconductor component with silicon wiring and method of fabricating the component.

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45. Nikitin, Ivan; Mahler, Joachim; Behrens, Thomas, Semiconductor device.

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46. Takeo Matsuki JP, Semiconductor device and capacitor with means to prevent deterioration due to hydrogen.

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47. Tanaka, Kazuo; Kumagai, Takashi; Karasawa, Junichi; Watanabe, Kunio, Semiconductor memory device and method of fabricating the same.

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48. Charles H. Dennison, Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections.

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49. Dennison, Charles H., Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry.

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50. Dennison, Charles H., Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry.

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51. Jigish D. Trivedi, Stacked local interconnect structure and method of fabricating same.

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52. Jigish D. Trivedi, Stacked local interconnect structure and method of fabricating same.

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53. Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.

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54. Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.

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55. Trivedi, Jigish D., Stacked local interconnect structure and method of fabricating same.

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56. Karp James, Structure and method for preventing barrier failure.

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57. Karp, James, Structure and method for preventing barrier failure.

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58. Sarigiannis,Demetrius; Meng,Shuang; Derderian,Garo J., Systems and methods for depositing material onto microfeature workpieces in reaction chambers.

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59. Kubista, David J.; Doan, Trung T.; Breiner, Lyle D.; Weimer, Ronald A.; Beaman, Kevin L.; Ping, Er-Xuan; Zheng, Lingyi A.; Basceri, Cem, Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers.

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60. Lin, Yung-Chi; Chen, Yi-Hsiu; Yang, Ku-Feng; Chiou, Wen-Chih, Through-substrate via formation with improved topography control.

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61. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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62. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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63. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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64. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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65. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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66. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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67. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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68. Jang Syun-Ming,TWX, Top metal and passivation procedures for copper damascene structures.

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