이 특허를 인용한 특허 (186)

1. Bhatt, Hemanshu; Vijay, Dilip; Pallinti, Jayanthi; Sun, Sey-Shing; Ying, Hong; Kao, Chiyi, Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing.

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2. Nikhil Vishwanath Kelkar ; Stephen A. Gee, Barrier pad for wafer level chip scale packages.

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3. Antol, Joze E.; Osenbach, John W.; Steiner, Kurt G., Bond pad support structure for semiconductor device.

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4. Saitoh Kazuto,JPX ; Shoji Reijiro,JPX, Bump structure, bump forming method and package connecting body.

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5. Lin, Charles Wen Chyang, Bumpless flip chip assembly with solder via.

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6. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips and via-fill.

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7. Lin Charles Wen Chyang,SGX, Bumpless flip chip assembly with strips and via-fill.

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8. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips-in-via and plating.

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9. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips-in-via and plating.

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10. Wark James M. ; Akram Salman, Carriers including projected contact structures for engaging bumped semiconductor devices.

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11. Lo, Jian-Wen; Chen, Chien-Fan, Chip having a metal pillar structure.

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12. Lin, Mou-Shiung; Lin, I, Shih-Hsiung, Chip package having a chip combined with a substrate via a copper pillar.

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13. Chen, Ke-Hung; Lin, Shih-Hsiung; Lin, Mou-Shiung, Chip package with dam bar restricting flow of underfill.

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14. Kuo, Nick; Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Chu-Fu, Chip structure with bumps and testing pads.

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15. Andry, Paul S.; Colgan, Evan G.; Wisnieff, Robert L., Composite wiring board with electrical through connections.

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16. Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Mou-Shiung, Connection between a semiconductor chip and a circuit component with a large contact area.

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17. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Cylindrical bonding structure and method of manufacture.

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18. Nguyen Tue ; Charneski Lawrence J. ; Hsu Sheng Teng, Differential copper deposition on integrated circuit surfaces.

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19. Jiang Tongbi, Electrical interconnection for attachment to a substrate.

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20. Jamin Ling ; Dave Charles Stepniak, Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor.

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21. Cohen, Uri, Electroplated metallic conductors.

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22. Kang, Dong-Min; Kang, Bo-Ram; Kim, Young-Nam; Lim, Young-Sam, Etching composition for an under-bump metallurgy layer.

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23. Ke, Chun-Chi; Huang, Chien-Ping, Fabrication method of semiconductor device having conductive bumps.

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24. Ke, Chun-Chi; Huang, Chien-Ping, Fabrication method of semiconductor device having conductive bumps.

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25. Lei, Kuolung; Shen, Tony; Samoranos, Susana; Wu, Te-Sung; Wang, Tsing-Chow, Flat-top bumping structure and preparation method.

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26. Charles W. C. Lin SG, Flip chip assembly with via interconnection.

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27. Charles W. C. Lin SG, Flip chip assembly with via interconnection.

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28. Okada Takashi,JPX ; Hirano Naohiko,JPX ; Tazawa Hiroshi,JPX ; Hosomi Eiichi,JPX ; Takubo Chiaki,JPX ; Doi Kazuhide,JPX ; Hiruta Yoichi,JPX ; Shibasaki Koji,JPX, Flip-chip connection type semiconductor integrated circuit device.

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29. Pace,Benedict G, High density electronic interconnection.

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30. Cohen, Uri, High speed electroplating metallic conductors.

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31. Antol, Joze Eura; Osenbach, John William; Weachock, Ronald James, Integrated circuit package including wire bonds.

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32. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.

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33. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.

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34. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Low fabrication cost, fine pitch and high reliability solder bump.

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35. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Low fabrication cost, fine pitch and high reliability solder bump.

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36. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.

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37. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.

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38. Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng; Lin, Chuen-Jye, Low fabrication cost, high performance, high reliability chip scale package.

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39. Lee,Jin Yuan; Lei,Ming Ta; Huang,Ching Cheng; Lin,Chuen Jye, Low fabrication cost, high performance, high reliability chip scale package.

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40. Wang, Chung-Yu; Huang, Chender; Tsao, Pei-Haw; Chen, Ken, Metal patterned structure for SiN surface adhesion enhancement.

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41. Lin, Mou-Shiung, Metallization structure over passivation layer for IC chip.

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42. Feustel, Frank; Frohberg, Kai; Werner, Thomas, Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom.

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43. Jian Li ; Xiao-Chun Mu ; Sridhar Balakrishnan, Method and an apparatus for forming an under bump metallization structure.

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44. Li Jian ; Mu Xiao-Chun ; Balakrishnan Sridhar, Method and an apparatus for forming an under bump metallization structure.

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45. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method for fabricating circuit component.

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46. Akram Salman, Method for fabricating microbump interconnect for bare semiconductor dice.

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47. Lin, Charles W. C., Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly.

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48. Kondo, Ichiharu; Ishihara, Yasuo; Nagahaka, Shuichi; Miyajima, Takeshi, Method for forming and patterning film.

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49. Wark, James M.; Akram, Salman, Method for making projected contact structures for engaging bumped semiconductor devices.

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50. Lin, Po Chun, Method for manufacturing a semiconductor structure.

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51. Mercer, Betty Shu; Shoemaker, Erika Leigh; Williams, Byron Lovell; Ng, Laurinda W.; Morton, Alec J.; Thompson, C. Matthew, Method for manufacturing an interconnect.

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52. Lei, Yi-Yang; Kuo, Hung-Jui; Liu, Chung-Shi, Method for reducing UBM undercut in metal bump structures.

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53. Nogami Takeshi ; Chan Simon, Method for reducing electromigration in a copper interconnect.

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54. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip.

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55. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a bumped compliant conductive trace to a semiconductor chip.

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56. Charles W. C. Lin SG; Cheng-Lien Chiang TW, Method of connecting a bumped conductive trace to a semiconductor chip.

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57. Lin, Charles W. C., Method of connecting a conductive trace and an insulative base to a semiconductor chip.

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58. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.

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59. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.

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60. Charles W. C. Lin SG, Method of connecting a conductive trace to a semiconductor chip.

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61. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip.

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62. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using a metal base.

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63. Lin,Charles W. C., Method of connecting a conductive trace to a semiconductor chip using conductive adhesive.

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64. Chiang, Cheng-Lien; Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching.

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65. Lin,Charles W. C.; Chiang,Cheng Lien, Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip.

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66. Lee, Chwan-Ying; Huang, Tzuen-Hsi, Method of electroless plating copper on nitride barrier.

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67. Lee, Jin-Yuan; Chou, Chien-Kang; Lin, Shih-Hsiung; Kuo, Hsi-Shan, Method of fabricating cylindrical bonding structure.

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68. Shoji Takashi,JPX ; Sakai Takekazu,JPX, Method of fabricating solder-bearing silicon semiconductor device and circuit board mounted therewith.

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69. Kang, Dong-Min; Kang, Bo-Ram; Kim, Young-Nam; Lim, Young-Sam, Method of forming a bump structure using an etching composition for an under bump metallurgy layer.

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70. Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.

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71. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.

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72. Lin, Shih-Hsiung; Lin, Mou-Shiung, Method of joining chips utilizing copper pillar.

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73. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a bumped terminal in a laminated structure for a semiconductor chip assembly.

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74. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly.

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75. Lin, Charles W. C., Method of making a pillar in a laminated structure for a semiconductor chip assembly.

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76. Charles W. C. Lin SG, Method of making a semiconductor chip assembly.

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77. Lin, Charles W. C., Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive.

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78. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a bumped metal pillar.

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79. Lin,Charles W. C.; Chen,Cheng Chung, Method of making a semiconductor chip assembly with a bumped terminal and a filler.

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80. Lin, Charles W. C.; Chen, Cheng-Chung, Method of making a semiconductor chip assembly with a bumped terminal, a filler and an insulative base.

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81. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a carved bumped terminal.

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82. Wang, Chia-Chung; Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace and a substrate.

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83. Charles W. C. Lin SG, Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.

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84. Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.

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85. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a laterally aligned bumped terminal and filler.

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86. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with a metal containment wall and a solder terminal.

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87. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with a precision-formed metal pillar.

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88. Chiang,Cheng Lien; Lin,Charles W. C., Method of making a semiconductor chip assembly with an embedded metal particle.

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89. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with an interlocked contact terminal.

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90. Lin, Charles W. C., Method of making a semiconductor chip assembly with chip and encapsulant grinding.

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91. Lin, Charles W. C.; Wang, Chia-Chung; Sigmond, David M., Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment.

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92. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding.

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93. Jiang Tongbi, Method of making a semiconductor device for attachment to a semiconductor substrate.

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94. Koyama, Mitsutoshi; Shimizu, Toshio; Kubota, Takeshi, Method of making a semiconductor device having a multilayer metal film of titanium/titanium nitride/tungsten/tungsten carbide.

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95. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.

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96. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.

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97. Charles W. C. Lin SG, Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly.

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98. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture.

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99. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture.

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100. Jiang, Tongbi, Method of making electrical interconnection for attachment to a substrate.

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101. Yoda, Tsuyoshi; Akagawa, Suguru, Method of manufacturing substrate joint body, substrate joint body and electrooptical device.

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102. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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103. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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104. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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105. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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106. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.

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107. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.

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108. Wark,James M.; Akram,Salman, Methods of making projected contact structures for engaging bumped semiconductor devices.

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109. Akram Salman, Microbump interconnect for semiconductor dice.

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110. Wang Tsing-Chow, Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties.

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111. Wang, Tsing-Chow, Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties.

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112. Mori, Hiroyuki; Kawasaki, Kazushige, Printed wiring board and method for manufacturing the same.

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113. Mori, Hiroyuki; Kawasaki, Kazushige, Printed wiring board and method for manufacturing the same.

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114. Uzoh Cyprian E., Process for forming a copper-containing film.

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115. Wark James M. ; Akram Salman, Projected contact structure for bumped semiconductor device and resulting articles and assemblies.

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116. Wark,James M.; Akram,Salman, Projected contact structures for engaging bumped semiconductor devices and methods of making the same.

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117. Wark,James M.; Akram,Salman, Projected contact structures for engaging bumped semiconductor devices and methods of making the same.

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118. Huang, Ching-Cheng; Lin, Chuen-Jye; Lei, Ming-Ta; Lin, Mou-Shiung, Reliable metal bumps on top of I/O pads after removal of test probe marks.

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119. Mou-Shiung Lin TW, Reliable metal bumps on top of I/O pads with test probe marks.

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120. Archer, III, Vance D.; Ayukawa, Michael C.; Bachman, Mark A.; Chesire, Daniel P.; Kang, Seung H.; Kook, Taeho; Merchant, Sailesh M.; Steiner, Kurt G., Routing under bond pad for the replacement of an interconnect layer.

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121. Charles W. C. Lin SG, Semiconductor chip assembly with ball bond connection joint.

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122. Lin, Charles W. C.; Chiang, Cheng-Lien, Semiconductor chip assembly with bumped conductive trace.

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123. Lin, Charles W.C.; Chiang, Cheng-Lien, Semiconductor chip assembly with bumped conductive trace.

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124. Lin,Charles W. C.; Chiang,Cheng Lien, Semiconductor chip assembly with bumped metal pillar.

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125. Charles W. C. Lin SG, Semiconductor chip assembly with bumped molded substrate.

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126. Lin,Charles W. C.; Chen,Cheng Chung, Semiconductor chip assembly with bumped terminal and filler.

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127. Lin, Charles W. C.; Chen, Cheng Chung, Semiconductor chip assembly with bumped terminal, filler and insulative base.

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128. Lin,Charles W. C.; Chiang,Cheng Lien, Semiconductor chip assembly with carved bumped terminal.

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129. Wang, Chia-Chung; Lin, Charles W. C., Semiconductor chip assembly with chip in substrate cavity.

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130. Lin, Charles W. C., Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit.

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131. Chiang,Cheng Lien; Lin,Charles W. C., Semiconductor chip assembly with embedded metal particle.

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132. Leu,Chuen Rong; Lin,Charles W. C., Semiconductor chip assembly with embedded metal pillar.

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133. Leu,Chuen Rong; Lin,Charles W. C., Semiconductor chip assembly with embedded metal pillar.

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134. Lin, Charles W. C., Semiconductor chip assembly with hardened connection joint.

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135. Lin, Charles W. C., Semiconductor chip assembly with interlocked conductive trace.

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136. Lin, Charles W.C., Semiconductor chip assembly with interlocked conductive trace.

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137. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with interlocked contact terminal.

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138. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Semiconductor chip assembly with laterally aligned bumped terminal and filler.

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139. Lin,Charles W. C.; Chen,Cheng Chung, Semiconductor chip assembly with laterally aligned filler and insulative base.

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140. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with metal containment wall and solder terminal.

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141. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with precision-formed metal pillar.

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142. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.

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143. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.

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144. Charles W. C. Lin SG, Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint.

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145. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint.

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146. Lin,Charles W. C., Semiconductor chip assembly with welded metal pillar.

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147. Lin, Charles W. C.; Chen, Cheng-Chung, Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal.

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148. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with welded metal pillar of stacked metal balls.

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149. Lin,Charles W. C., Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond.

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150. Chou, Chiu-Ming; Chou, Chien-Kang; Lin, Ching-San; Lin, Mou-Shiung, Semiconductor chip with passivation layer comprising metal interconnect and contact pads.

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151. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.

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152. Lin, Mou-Shiung; Lo, Hsin-Jung; Chou, Chien-Kang; Chou, Chiu-Ming; Lin, Ching-San, Semiconductor chip with post-passivation scheme formed over passivation layer.

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153. Theuss, Horst, Semiconductor component with connecting elements and method for producing the same.

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154. Fujii, Teruyuki; Hanaoka, Kazuya, Semiconductor device.

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155. Lo, Jian-Wen; Chen, Chien-Fan, Semiconductor device.

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156. Nemoto, Yoshihiko, Semiconductor device.

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157. Norio Okada JP, Semiconductor device and method for manufacturing the same.

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158. Yanagida, Toshiharu, Semiconductor device and method of fabricating the same.

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159. Yanagida, Toshiharu, Semiconductor device and method of fabricating the same.

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160. Matsuo, Mie; Miyata, Masahiro; Ezawa, Hirokazu, Semiconductor device and method of manufacturing the same.

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161. Nakatani, Goro, Semiconductor device and method of manufacturing the same.

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162. Kurosawa, Yasunori, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.

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163. Kurosawa,Yasunori, Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument.

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164. Tongbi Jiang, Semiconductor device for attachment to a semiconductor substrate.

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165. Ke, Chun-Chi; Huang, Chien-Ping, Semiconductor device having conductive bumps and deviated solder pad.

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166. Ke, Chun-Chi; Huang, Chien-Ping, Semiconductor device having conductive bumps, metallic layers, covering layers and fabrication method thereof.

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167. Tago, Masamoto; Tomita, Yoshihiro; Takahashi, Kenji, Semiconductor device with a binary alloy bonding layer.

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168. Nishiyama,Tomohiro; Tago,Masamoto, Semiconductor element including a wet prevention film.

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169. Wang, Sheng-Ming; Feng, Hsiang-Ming; Kuo, Yen-Hua, Semiconductor package substrates having layered circuit segments, and related methods.

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170. Shih, Meng-Kai; Lee, Chang-Chi, Semiconductor package with integrated metal pillars and manufacturing methods thereof.

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171. Lin, Po Chun, Semiconductor structure and manufacturing method thereof.

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172. Shoji Takashi,JPX ; Sakai Takekazu,JPX, Silicon semiconductor device,electrode structure therefor, and circuit board mounted therewith.

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173. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Misra, Ekta; Muzzy, Christopher D.; Sauter, Wolfgang; Scott, George J., Solder bump connections.

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174. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Misra, Ekta; Muzzy, Christopher D.; Sauter, Wolfgang; Scott, George J., Solder bump connections.

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175. Bachman, Mark A.; Bitting, Donald S.; Chittipeddi, Sailesh; Kang, Seung H.; Merchant, Sailesh M., Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore.

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176. Lin, Mou-Shiung, Solder interconnect on IC chip.

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177. Weng, Cheng-Yi, Stacked semiconductor packages and related methods.

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178. Lin, Mou-Shiung; Lei, Ming-Ta; Lin, Chuen-Jye, Structure and manufacturing method of a chip scale package.

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179. Chen, Tien-Szu; Lee, Chun-Che; Wang, Sheng-Ming, Substrate for semiconductor package and process for manufacturing.

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181. Chen, Tien-Szu; Lee, Chun-Che; Wang, Sheng-Ming, Substrate for semiconductor package and process for manufacturing.

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182. Lin, Charles W. C., Support circuit with a tapered through-hole for a semiconductor chip assembly.

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183. Dalal, Hormazdyar Minocher; Prasad, Jagdish; Ziad, Hocine Bouzid, Thick metal interconnect with metal pad caps at selective sites and process for making the same.

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184. Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A., Thick plated interconnect and associated auxillary interconnect.

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185. Lin,Charles W. C.; Chiang,Cheng Lien, Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture.

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186. Test, Howard R.; Amador, Gonzalo; Subido, Willmar E., Wire bonding process for copper-metallized integrated circuits.

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