초록 ▼

The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps invo

The present invention is directed to a technology that simplifies the process of fabricating multilayer interconnects and reduces capacitance in integrated circuits employing multilayer interconnects. The novel landing pad technology of the present invention simplifies the current process steps involved in the formation of multilayer interconnects. The same contact/via etch, the same PVD TiN deposition, etc., can be modularized and repeated to build up multilayer metalization. The process of the present invention for forming multilayer interconnects involves the formation of Ti/TiN stack interconnect structures that can be used as local interconnects and contact landing pads on the same level. The contact landing pads facilitate the use of a borderless contact approach which enables a reduction in the size of the source-drain area. As the source-drain area is reduced, junction capacitance decreases, and packing density can be increased. Source-drain real estate can be also be minimized by using the Ti/TiN stack interconnect structures as contact landing pads in the implementation of raised source-drain technology. The Ti/TiN stack interconnect structures can also be used as short local interconnects in SRAM devices.

대표청구항 ▼

A process for forming multilayer interconnects for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said process comprising: (a) forming a layer of Ti on said insulating regions and said conductive regions; (b) forming a firs

A process for forming multilayer interconnects for connecting conductive regions to conductive regions separated by insulating regions supported on a semiconductor substrate, said process comprising: (a) forming a layer of Ti on said insulating regions and said conductive regions; (b) forming a first layer of TiN on said layer of Ti; (c) patterning and etching said layer of Ti and said first layer of TiN to form at least one Ti/TiN stack interconnect structure selected from the group consisting of (1) a contact landing pad contacting one of said conductive regions, (2) a local interconnect contacting at least two of said conductive regions, forming electrical connection therebetween, and (3) a local interconnect contacting at least one of said conducting regions and comprising at least one contact landing pad, forming electrical connection therebetween; (d) forming an interlayer dielectric over said semiconductor substrate; (e) etching contact openings in said interlayer dielectric down to at least one of said contact landing pads or one of said local interconnects, each of said contact openings having a bottom and sidewalls; (f) depositing a second layer of TiN such that said second layer of TiN is formed on said bottom and said sidewalls of said contact openings; (g) depositing a layer of metal thereby filling said contact openings with said layer of metal; (h) removing said second layer of TiN and said layer of metal outside of said contact openings thereby forming metal plugs in said contact openings; and (i) forming a first layer of metal interconnects on said interlayer dielectric contacting said metal plugs.