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Method for forming polish stop layer for CMP process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/316
출원번호 US-0720638 (1996-10-02)
발명자 / 주소
  • Jang Syun-Ming (Hsin-chu TWX) Yu Chen-Hua (Hsin-chu TWX)
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-chu TWX 03)
인용정보 피인용 횟수 : 51  인용 특허 : 3

초록

A method is disclosed for planarizing interlevel dielectric layers in semiconductor wafers extremely smoothly. The key aspect of the disclosure is a buried stop layer that is ion implanted into the interlevel layer. It is shown that the stop layer can be formed at precise depths from the surface of

대표청구항

A method of forming a polish stop layer for chemical/mechanical polishing (CMP) of semiconductor wafers comprising the steps of: providing a wiring layer comprising aluminum on said wafer; providing an oxide layer on said wiring layer; ion implanting atoms in said oxide layer to form a polish stop l

이 특허에 인용된 특허 (3)

  1. Jaso Mark A. (Yorktown Heights NY) Jones Paul B. (Wappingers Falls NY) Meyerson Bernard S. (Yorktown Heights NY) Patel Vishnubhai V. (Yorktown Heights NY), CVD diamond or diamond-like carbon for chemical-mechanical polish etch stop.
  2. Komatsu Shigeru (Yokohama JPX) Nakamura Michio (Kawasaki JPX), Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions.
  3. Lee Chii-Chang (Austin TX) Kawasaki Hisao (Austin TX), Process for forming a semiconductor device including conductive members.

이 특허를 인용한 특허 (51)

  1. Daniel David W. ; Gregory John W. ; Allman Derryl D. J., Apparatus and method of detecting a polishing endpoint layer of a semiconductor wafer which includes a metallic reporting substance.
  2. Taravade Kunal N., Apparatus for detecting an endpoint polishing layer of a semiconductor wafer having a wafer carrier with independent concentric sub-carriers and associated method.
  3. Berman Michael J., Automated inspection system for residual metal after chemical-mechanical polishing.
  4. Berman, Michael J., Determination of film thickness during chemical mechanical polishing.
  5. Wu, Yung-Hsu; Lu, Hsin-Hsien; Bao, Tien-I; Shue, Shau-Lin, Dielectric protection layer as a chemical-mechanical polishing stop layer.
  6. Lee Tzung-Han,TWX ; Lu Tse-Yi,TWX, Dual damascene method comprising ion implanting to densify dielectric layer and forming a hard mask layer with a tapered opening.
  7. Gail D. Shelton ; Gayle W. Miller, Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint.
  8. Shelton Gail D. ; Miller Gayle W., Endpoint detection method and apparatus which utilize a chelating agent to detect a polishing endpoint.
  9. Chisholm Brynne K. ; Miller Gayle W. ; Shelton Gail D., Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material.
  10. Chisholm Brynne K. ; Miller Gayle W. ; Shelton Gail D., Endpoint detection method and apparatus which utilize an endpoint polishing layer of catalyst material.
  11. Inoue, Yasunori; Okayama, Yoshio, Fabrication method of semiconductor device and abrasive liquid used therein.
  12. He Yue Song ; Liu Yowjuang William, High density isolation using an implant as a polish stop.
  13. Ogawa,Tsuyoshi, High-frequency circuit block, its manufacturing method, high-frequency module device, and its manufacturing method.
  14. Osugi Richard S. ; Nagahara Ronald J. ; Lee Dawn M., In-situ chemical-mechanical polishing slurry formulation for compensation of polish pad degradation.
  15. Seliskar John J. ; Allman Derryl D. J. ; Gregory John W. ; Yakura James P. ; Kwong Dim Lee, Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region.
  16. Guthrie,Hung Chin; Jiang,Ming, Manufacturing method for forming a write head top pole using chemical mechanical polishing with a DLC stop layer.
  17. Inoue, Yasunori; Mizuhara, Hideki, Manufacturing method of semiconductor device including an insulation film on a conductive layer.
  18. Hiroshi Mizuno JP; Osamu Kinoshita JP; Tetsuaki Murohashi JP; Akihisa Ueno JP; Yoshifumi Sakuma JP; Kostas Amberiadis, Method and apparatus for chemical-mechanical polishing.
  19. Berman Michael J. ; Holland Karey L., Method and apparatus for concurrent pad conditioning and wafer buff in chemical mechanical polishing.
  20. Allman Derryl D. J. ; Daniel David W. ; Gregory John W., Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system.
  21. Derryl D. J. Allman ; David W. Daniel ; John W. Gregory, Method and apparatus for detecting a planarized outer layer of a semiconductor wafer with a confocal optical system.
  22. Allman Derryl D. J. ; Daniel David W. ; Chisholm Michael F., Method and apparatus for detecting a polishing endpoint based upon heat conducted through a semiconductor wafer.
  23. Allman Derryl D. J. ; Daniel David W. ; Gregory John W., Method and apparatus for detecting a polishing endpoint based upon infrared signals.
  24. Taravade Kunal N., Method and apparatus for detecting an endpoint polishing layer by transmitting infrared light signals through a semiconductor wafer.
  25. Miller Gayle W. ; Chisholm Michael F., Method and apparatus for detecting an ion-implanted polishing endpoint layer within a semiconductor wafer.
  26. Nagahara Ronald J. ; Lee Dawn M., Method and apparatus for using across wafer back pressure differentials to influence the performance of chemical mechanical polishing.
  27. Nagahara, Ronald J.; Lee, Dawn M., Method and apparatus for using across wafer back pressure differentials to influence the performance of chemical mechanical polishing.
  28. Jiang, Li; Li, Mingqi, Method for fabricating a high-K metal gate MOS.
  29. Hachiya Takayo,JPX ; Yabuki Moto,JPX ; Kamijou Hiroyuki,JPX, Method for manufacturing a semiconductor device.
  30. Hsia Shouli Steve ; Wang Yanhua ; Pallinti Jayanthi, Method for shallow trench isolations with chemical-mechanical polishing.
  31. Miller Gayle W. ; Shelton Gail D. ; Chisholm Brynne K., Method of detecting a polishing endpoint layer of a semiconductor wafer which includes a non-reactive reporting specie.
  32. Gardner Mark I. ; Kadosh Daniel, Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines.
  33. Richter, Ralf; Foltyn, Thomas; Mowry, Anthony, Method of forming an interlayer dielectric material having different removal rates during CMP.
  34. Niu Pao-Kang,TWX ; Lee Chang-Sheng,TWX ; Lin Bih-Tiao,TWX ; Lee Sen-Nan,TWX, Method of planarization.
  35. Shiu Hao-Kuang,TWX ; Wu Kun-Lin,TWX ; Lu Horng-Bor,TWX ; Lin Jenn-Tarng,TWX, Method of planarization using interlayer dielectric.
  36. Schatz Kenneth D. ; Huff Brett, Method of planarizing by polishing a structure which is formed to promote planarization.
  37. Yen, Yu-Ting; Chen, Ying-Ho, Planarization method, method for manufacturing semiconductor structure, and semiconductor structure.
  38. Ohkubo Yasunori,JPX, Process for the production of semiconductor substrate having silicon-on-insulating structure and process for the production of semiconductor device.
  39. Gabric Zvonimir,DEX ; Spindler Oswald,DEX ; Grassl Thomas,DEX, Production method for an insulation layer functioning as an intermetal dielectric.
  40. Watanabe, Hiroyuki; Mizuhara, Hideki; Tanimoto, Shinichi; Nishida, Atsuhiro; Yamaoka, Yoshikazu; Inoue, Yasunori, Semiconductor device and fabrication method thereof.
  41. Matsubara, Naoteru; Mizuhara, Hideki; Goto, Takashi, Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer.
  42. Mizuhara Hideki,JPX ; Watanabe Hiroyuki,JPX ; Matsubara Naoteru,JPX, Semiconductor device including insulation film and fabrication method thereof.
  43. Mizuhara, Hideki; Watanabe, Hiroyuki; Matsubara, Naoteru, Semiconductor device including insulation film and fabrication method thereof.
  44. Xie, Xin Yun, Semiconductor structure and fabrication method thereof.
  45. Shouli Steve Hsia ; Yanhua Wang ; Jayanthi Pallinti, Shallow trench isolation chemical-mechanical polishing process.
  46. Nguyen, Loi; Sundaresan, Ravishankar, Sram cell fabrication with interlevel Dielectric planarization.
  47. Allman, Derryl D. J.; Gregory, John W., Substrate planarization with a chemical mechanical polishing stop layer.
  48. Wu, Yung-Hsu; Fu, Shih-Kang; Yao, Hsin-Chieh; Lee, Hsiang-Huan; Lee, Chung-Ju; Chen, Hai-Ching; Shue, Shau-Lin, System and method for chemical-mechanical planarization of a metal layer.
  49. Dou-I Chen TW; Jr-Hong Chen TW; Pi-Fu Chen TW; Wung-Ui Huang TW, Thin film transistor (TFT) structure with planarized gate electrode.
  50. Yu Chen-Hua,TWX ; Jang Syun-Ming,TWX ; Shih Tsu,TWX ; Yen Anthony,TWX ; Twu Jih-Churng,TWX, Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish.
  51. Chen-Hua Yu TW; Syun-Ming Jang TW; Tsu Shih TW; Anthony Yen TW; Jih-Chuyng Twu TW, Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish.
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