초록 ▼

A single instruction multiple data stream (“SIMD”) processor includes multiple processing elements (“PEs”). Each PE includes a memory, a first multiplexer, an instruction register, a local instruction buffer for storing an instruction and a unit for modifying the instruction, in its entirety, to cre

A single instruction multiple data stream (“SIMD”) processor includes multiple processing elements (“PEs”). Each PE includes a memory, a first multiplexer, an instruction register, a local instruction buffer for storing an instruction and a unit for modifying the instruction, in its entirety, to create a modified instruction. The modified instruction is stored in the local instruction buffer until it is executed. This structure modifies the instruction broadcast from the central controller of an SIMD computer in its entirety and creates modified instructions which can be unique to each PE.

대표청구항 ▼

A single instruction multiple data stream (SIMD) array processor, comprising: a plurality of processing elements (PEs), each for receiving an instruction broadcasted from an external source, each of said plurality of processing elements including: a memory for storing data therein; a first multiplex

A single instruction multiple data stream (SIMD) array processor, comprising: a plurality of processing elements (PEs), each for receiving an instruction broadcasted from an external source, each of said plurality of processing elements including: a memory for storing data therein; a first multiplexer for receiving said broadcasted instruction; an instruction register, coupled to said memory and to said first multiplexer, for receiving an output from said first multiplexer and for providing control signals and an output to said memory; storage means, coupled to said instruction register and to said memory, for storing at least one instruction, said at least one instruction comprising data read out of the memory and placed in the storage means, said first multiplexer further receiving said at least one instruction in said storage means; and means for modifying said at least one instruction in its entirety to respectively create a modified instruction and storing said modified instruction in said storage means to be executed as a next instruction, said modified instruction being used repeatedly when selected by said broadcasted instruction from said external source, said modifying means including means for selecting one of said broadcasted instruction and said modified instruction to be output to said instruction register, wherein a first PE of said PEs modifies said at least one instruction differently than a second PE of said PEs and said first PE modifies a first portion of said at least one instruction and said second PE modifies a second portion of said at least one instruction.