이 특허를 인용한 특허 (250)

1. Sherrer, David W.; Rollin, Jean-Marc, Batch fabricated microconnectors.

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2. Sherrer, David W.; Rollin, Jean-Marc, Batch fabricated microconnectors.

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3. Adams, Scott G.; Davis, Tim, Boundary isolation for microelectromechanical devices.

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4. Forbes, Leonard, Capacitive techniques to reduce noise in high speed interconnections.

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5. Forbes,Leonard, Capacitive techniques to reduce noise in high speed interconnections.

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6. Akram,Salman, Carrier for wafer-scale package and wafer-scale package including the carrier.

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7. Akram, Salman, Carrier for wafer-scale package, wafer-scale package including the carrier, and methods.

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8. Pogge, H. Bernhard; Yu, Roy; Prasad, Chandrika; Narayan, Chandrasekhar, Chip and wafer integration process using vertical connections.

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9. Pogge,H. Bernhard; Yu,Roy; Prasad,Chandrika; Narayan,Chandrasekhar, Chip and wafer integration process using vertical connections.

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10. Dujari, Prateek; Monzon, Franklin; Tadayon, Pooya, Chip package enabling increased input/output density.

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11. Glenn, Thomas P.; Webster, Steven; DiCaprio, Vincent, Chip size semiconductor packages with stacked dies.

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12. Kang, Sun-Won; Baek, Seung-Duk; Lee, Jong-Joo, Chip stack package.

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13. Kang, Sun-Won; Baek, Seung-Duk; Lee, Jong-Joo, Chip stack package.

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14. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Coaxial integrated circuitry interconnect lines, and integrated circuitry.

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15. Sherrer, David, Coaxial transmission line microstructure with a portion of increased transverse dimension and method of formation thereof.

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16. Sherrer, David W.; Fisher, John J., Coaxial waveguide microstructure having center and outer conductors configured in a rectangular cross-section.

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17. Sherrer, David W.; Fisher, John J., Coaxial waveguide microstructures having an active device and methods of formation thereof.

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18. Sherrer, David W.; Fisher, John J., Coaxial waveguide microstructures having conductors formed by plural conductive layers.

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19. Bertin, Claude Louis; Kelley, Gordon Arthur; Schmidt, Dennis Arthur; Tonti, William Robert; Zalesinski, Jerzy Maria, Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality.

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20. Claude Louis Bertin ; Gordon Arthur Kelley ; Dennis Arthur Schmidt ; William Robert Tonti ; Jerzy Maria Zalesinski, Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality.

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21. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Compact system module with built-in thermoelectric cooling.

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22. Ahn,Kie Y.; Forbes,Leonard; Cloud,Eugene H., Compact system module with built-in thermoelectric cooling.

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23. Ahn Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.

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24. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.

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25. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.

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26. Oh, Tae Seok; Kim, Jong Hong, Coplanarity inspection system of package and method thereof.

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27. Forbes, Leonard; Ahn, Kie Y., Current mode signal interconnects and CMOS amplifier.

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28. Tuan, Tim; Chung, Daniel; Cline, Ronald; DeBaets, Andy; Klein, Matthew H., Device specific configuration of operating voltage.

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29. Sherrer, David W.; Reid, James R., Devices and methods for solder flow control in three-dimensional microstructures.

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30. Sherrer, David W.; Reid, Jr., James R., Devices and methods for solder flow control in three-dimensional microstructures.

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31. Pratt, Dave, Die stacking with an annular via having a recessed socket.

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32. Pratt, Dave, Die stacking with an annular via having a recessed socket.

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33. Pratt, Dave, Die stacking with an annular via having a recessed socket.

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34. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.

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35. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.

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36. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.

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37. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.

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38. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.

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39. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking with leads extending along edges.

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40. Dobritz, Stephan; Polaczyk, Christoph; Irsigler, Roland, Electric device, stack of electric devices, and method of manufacturing a stack of electric devices.

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41. Winderl, Johann, Electronic component with stacked semiconductor chips.

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42. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Electronic systems using optical waveguide interconnects formed through a semiconductor wafer.

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43. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer.

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44. Adams,Scott; Davis,Tim; Miller,Scott; Shaw,Kevin; Chong,John Matthew; Lee,Seung (Chris) Bok, Electrostatic actuator for microelectromechanical systems and methods of fabrication.

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45. Adams,Scott; Davis,Tim; Miller,Scott; Shaw,Kevin; Chong,John Matthew; Lee,Seung Bok (Chris), Electrostatic actuator for microelectromechanical systems and methods of fabrication.

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46. Patti, Robert; Hong, Sangki; Ramasamy, Chockalingam, Fiducial scheme adapted for stacked integrated circuits.

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47. Gaul, Stephen Joseph; Hebert, Francois, Heat conduction for chip stacks and 3-D circuits.

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48. Kie Y. Ahn ; Leonard Forbes ; Paul Farrar, High performance packaging for microprocessors and DRAM chips which minimizes timing skews.

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49. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability layered films to reduce noise in high speed interconnects.

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50. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.

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51. Badehi, Avner, Integrated circuit device.

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52. Badehi, Avner, Integrated circuit device.

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53. Badehi, Avner, Integrated circuit device.

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54. Salatino Matthew M. ; Studebaker S. James ; VanVonno Nicolaas W., Integrated circuit device having an opening exposing the integrated circuit die and related methods.

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55. Kwon, Youngwoo; Chung, Ki Woong, Integrated circuit module package and assembly method thereof.

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56. Hsuan, John Min-Chih, Integrated circuit with improved interconnect structure and process for making same.

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57. Hsuan, Min-Chih John, Integrated circuit with improved interconnect structure and process for making same.

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58. Hsuan,Min Chih John, Integrated circuit with improved interconnect structure and process for making same.

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59. Min-Chih John Hsuan TW, Integrated circuit with improved interconnect structure and process for making same.

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60. Ahn Kie Y., Integrated circuitry and methods of forming integrated circuitry.

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61. Kie Y. Ahn, Integrated circuitry having conductive passageway interconnecting circuitry on front and back surfaces of a wafer fragment.

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62. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same.

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63. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer.

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64. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.

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65. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.

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66. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.

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67. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.

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68. Geusic,Joseph E.; Ahn,Kie Y.; Forbes,Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.

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69. Rollin, Jean-Marc; Sherrer, David W., Integrated electronic components and methods of formation thereof.

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70. Rollin, Jean-Marc; Sherrer, David W., Integrated electronic components and methods of formation thereof.

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71. Shi, Wei; Lu, Daoqiang; Bai, Yiqun; Zhou, Qing A.; He, Jianqqi, Integrated micro-channels for 3D through silicon architectures.

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72. Lu,Szu Wei; Tzou,Jerry, Interconnect structure for semiconductor package.

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73. Fay, Owen R.; Farnworth, Warren M.; Hembree, David R., Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods.

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74. Fay, Owen R.; Farnworth, Warren M.; Hembree, David R., Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods.

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75. Fay, Owen R.; Farnworth, Warren M.; Hembree, David R., Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods.

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76. Fay, Owen R.; Farnworth, Warren M.; Hembree, David R., Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods.

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77. Hsuan,Min Chih John, Intermediate structure for making integrated circuit device and wafer.

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78. Akram,Salman, Interposers for chip-scale packages and intermediates thereof.

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79. Vincent DiCaprio ; Sean T. Crowley ; J. Mark Bird, Low profile package for plural semiconductor dies.

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80. Anthony J. LoBianco ; Frank J. Juskey ; Stephen G. Shermer ; Vincent DiCaprio ; Thomas P. Glenn, Making semiconductor packages with stacked dies and reinforced wire bonds.

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81. Noma, Takashi; Shinogi, Hiroyuki; Suzuki, Akira; Seki, Yoshinori; Kuhara, Koichi; Takao, Yukihiro; Yamada, Hiroshi, Manufacturing method of semiconductor device.

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82. Di Stefano, Thomas H.; Di Stefano, Peter T., Method and apparatus for aligning and/or leveling a test head.

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83. Di Stefano, Thomas H.; Di Stefano, Peter T., Method and apparatus for aligning and/or leveling a test head.

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84. In't Veld,Frederik Hendrik; Savenije,Johannes Hermanus, Method and apparatus for manufacturing a packaged semiconductor device, packaged semiconductor device obtained with such a method and metal carrier suitable for use in such a method.

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85. Rahman, Arifur, Method and apparatus for programmable heterogeneous integration of stacked semiconductor die.

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86. Tsai,Chen Jung; Lin,Chih Wen, Method and apparatus for stacking electrical components using via to provide interconnection.

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87. Uzoh, Cyprian Emeka; Monadgemi, Pezhman; Caskey, Terrence; Ayatollahi, Fatima Lina; Haba, Belgacem; Woychik, Charles G.; Newman, Michael, Method and structures for heat dissipating interposers.

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88. Lott, James A.; Ledentsov, Nikolai; Shchukin, Vitaly, Method for attaching optical components onto silicon-based integrated circuits.

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89. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer.

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90. Soh, Hyongsok, Method for interconnecting arrays of micromechanical devices.

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91. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Method for making multilayered coaxial interconnect structure.

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92. Ahrens, Carsten; Schuderer, Berthold; Willkofer, Stefan, Method for producing a connection region on a side wall of a semiconductor body.

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93. Krüger, Olaf; Würfl, Joachim; Schöne, Gerd, Method for producing vertical electrical contact connections in semiconductor wafers.

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94. Kwon, Yong-Chai; Lee, Dong-Ho, Method of fabricating semiconductor package structure.

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95. Haba, Belgacem; Mohammed, Ilyas, Method of fabricating stacked assembly including plurality of stacked microelectronic elements.

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96. Haba, Belgacem, Method of fabricating stacked packages with bridging traces.

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97. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method of forming an optical fiber interconnect through a semiconductor wafer.

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98. Rahman, Arifur, Method of forming stacked-die integrated circuit.

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99. Glenn, Thomas P.; Smith, Lee J.; Zoba, David A.; Ramakrishna, Kambhampati; DiCaprio, Vincent, Method of making a semiconductor package including stacked semiconductor dies.

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100. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.

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101. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.

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102. Kameyama, Koujiro; Suzuki, Akira; Oikawa, Takahiro, Method of manufacturing semiconductor device.

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103. Noma, Takashi; Shinogi, Hiroyuki; Takai, Nobuyuki; Kitagawa, Katsuhiko; Tokushige, Ryoji; Otagaki, Takayasu; Ando, Tatsuya; Okigawa, Mitsuru, Method of manufacturing semiconductor device with wiring on side surface thereof.

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104. Yasuo Nakatani JP, Method of manufacturing semiconductor device, and semiconductor device manufactured thereby.

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105. Subramanian,Kanakasabapathi; Fortin,Jeffrey Bernard; Tian,Wei Cheng, Method of wet etching vias and articles formed thereby.

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106. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.

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107. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.

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108. Sinha, Nishant, Methods for forming conductive vias in semiconductor device components.

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109. Sherrer, David W.; Cardwell, Dara L., Methods of fabricating electronic and mechanical structures.

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110. Farnworth, Warren M.; McDonald, Steven M.; Sinha, Nishant; Hiatt, William M., Methods of fabricating substrates including at least one conductive via.

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111. Farnworth,Warren M.; McDonald,Steven M.; Sinha,Nishant; Hiatt,William M., Methods of fabricating substrates including at least one conductive via.

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112. Farnworth, Warren M.; McDonald, Steven M.; Sinha, Nishant; Hiatt, William M., Methods of fabricating substrates including one or more conductive vias.

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113. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Methods of forming coaxial integrated circuitry interconnect lines.

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114. Akram, Salman; Wark, James M.; Hiatt, William Mark, Methods of forming interconnects and semiconductor structures.

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115. Akram, Salman; Wark, James M.; Hiatt, William M., Methods of forming interconnects in a semiconductor structure.

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116. Haba, Belgacem, Methods of forming semiconductor stacked die devices.

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117. Wang Tsing-Chow, Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties.

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118. Wang, Tsing-Chow, Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties.

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119. Rollin, Jean-Marc; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken; Oliver, J. Marcus; Smith, Tim, Microstructure including microstructural waveguide elements and/or IC chips that are mechanically interconnected to each other.

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120. Reid, James Robert, Multi-layer digital elliptic filter and method.

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121. Reid, James Robert, Multi-layer digital elliptic filter and method.

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122. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Multi-layered coaxial interconnect structure.

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123. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.

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124. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.

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125. Hayasaka, Nobuo; Okumura, Katsuya; Sasaki, Keiichi; Matsuo, Mie, Multichip semiconductor device, chip therefor and method of formation thereof.

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126. Hayasaka,Nobuo; Okumura,Katsuya; Sasaki,Keiichi; Matsuo,Mie, Multichip semiconductor device, chip therefor and method of formation thereof.

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127. Kwon, Youngwoo; Chung, Ki Woong, Multilayer integrated circuit for RF communication and method for assembly thereof.

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128. Kwon,Youngwoo; Chung,Ki Woong, Multilayer integrated circuit for RF communication and method for assembly thereof.

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129. Foster, Donald C., Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring.

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130. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip VIAS in stacked chips.

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131. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura, Off-chip vias in stacked chips.

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132. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.

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133. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.

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134. Il Kwon Shim SG; Vincent DiCaprio ; Paul Hoffman ; Byung Joon Han SG, Package for stacked integrated circuits.

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135. Jiang, Tongbi; Chia, Yong Poo, Packaged integrated circuit devices with through-body conductive vias, and methods of making same.

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136. Jiang, Tongbi; Chia, Yong Poo, Packaged integrated circuit devices with through-body conductive vias, and methods of making same.

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137. Jiang, Tongbi; Poo, Chia Yong, Packaged integrated circuit devices with through-body conductive vias, and methods of making same.

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138. Kobachi Mitsuo,JPX ; Fujita Akihiro,JPX ; Hasegawa Naoto,JPX, Photoreflective detector including a light emitting element and a light receiving element located at different distances from an object reflecting light from the emitting element.

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139. Sinha,Nishant, Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias.

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140. Bieck, Dipl.-Ing. Florian; Leib, Jürgen, Process for making contact with and housing integrated circuits.

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141. Bieck, Dipl.-Ing. Florian; Leib, Jürgen, Process for making contact with and housing integrated circuits.

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142. Bieck, Florian; Leib, Jürgen, Process for making contact with and housing integrated circuits.

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143. Kripesh, Vaidyanathan; Rotaru, Mihai Dragos; Periasamy, Ganesh Vetrivel; Yoon, Seung Uk; Nagarajan, Ranganathan, RF and MMIC stackable micro-modules.

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144. Kripesh,Vaidyanathan; Rotaru,Mihai Dragos; Periasamy,Ganesh Vetrivel; Yoon,Seung Uk; Nagarajan,Ranganathan, RF and MMIC stackable micro-modules.

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145. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura, Reconstituted wafer stack packaging with after-applied pad extensions.

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146. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura Wills, Reconstituted wafer stack packaging with after-applied pad extensions.

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147. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.

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148. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.

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149. Pratt, David, Redistribution layers for microfeature workpieces, and associated systems and methods.

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150. Akram,Salman; Wark,James M.; Hiatt,William M., Selective nickel plating of aluminum, copper, and tungsten structures.

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151. Shi, Xunqing; Xie, Bin; Chung, Chang Hwa, Semiconductor chip with through-silicon-via and sidewall pad.

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152. Han, Jae-Won, Semiconductor device.

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153. Noma, Takashi; Shinogi, Hiroyuki; Takao, Yukihiro, Semiconductor device.

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154. Kurashima, Yohei; Umetsu, Kazushige; Ito, Haruki, Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment.

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155. Sinha, Nishant, Semiconductor device components with conductive vias and systems including the components.

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156. Fukasawa, Norio, Semiconductor device having a functional surface.

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157. Schoellkopf, Jean Pierre, Semiconductor device having several assembled integrated-circuit chips and method of assembling and electrically connecting the integrated-circuit chips.

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158. Shibata, Kayoko; Ikeda, Hiroaki, Semiconductor device including a plurality of semiconductor chips and a plurality of through-line groups.

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159. Shibata, Kayoko; Ikeda, Hiroaki, Semiconductor device including stacked semiconductor chips.

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160. Shibata, Kayoko; Ikeda, Hiroaki, Semiconductor device including stacked semiconductor chips.

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161. Shibata, Kayoko; Ikeda, Hiroaki, Semiconductor device including stacked semiconductor chips.

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162. Akram, Salman; Wark, James M.; Hiatt, William M., Semiconductor device structures including nickel plated aluminum, copper, and tungsten structures.

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163. Noma,Takashi; Shinogi,Hiroyuki; Takai,Nobuyuki; Kitagawa,Katsuhiko; Tokushige,Ryoji; Otagaki,Takayasu; Ando,Tatsuya; Okigawa,Mitsuru, Semiconductor device with holding member.

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164. Noma,Takashi; Shinogi,Hiroyuki; Takai,Nobuyuki; Kitagawa,Katsuhiko; Tokushige,Ryoji; Otagaki,Takayasu; Ando,Tatsuya; Okigawa,Mitsuru, Semiconductor device with sidewall wiring.

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165. Kirby, Kyle K.; Farnworth, Warren M., Semiconductor devices and in-process semiconductor devices having conductor filled vias.

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166. Akram, Salman; Wark, James M.; Hiatt, William Mark, Semiconductor devices comprising nickel- and copper-containing interconnects.

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167. Jackson,Timothy L.; Murphy,Tim E., Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods.

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168. Shin, Won Sun; Lee, Seon Goo; Chun, Do Sung; Jang, Tae Hoan; DiCaprio, Vincent D., Semiconductor package and method for fabricating the same.

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169. Shin,Won Sun; Chun,Do Sung; Lee,Sang Ho; Lee,Seon Goo; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.

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170. Shin,Won Sun; Chun,Do Sung; Lee,Soon Goo; Shim,Il Kwon; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.

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171. Shin,Won Sun; Lee,Seon Goo; Chun,Do Sung; Jang,Tae Hoan; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.

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172. WonSun Shin KR; DoSung Chun TH; SangHo Lee KR; SeonGoo Lee KR; Vincent DiCaprio, Semiconductor package and method for fabricating the same.

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173. Vo, Thao H. T.; Gan, Andy H.; Li, Xiao-Yu; Klein, Matthew H., Semiconductor package having IC dice and voltage tuners.

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174. Kang, Uk-Song, Semiconductor package having memory devices stacked on logic device.

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175. Kang, Uk-Song, Semiconductor package having memory devices stacked on logic device.

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176. Shin, WonSun; Chun, DoSung; Lee, SangHo; Lee, SeonGoo; DiCaprio, Vincent, Semiconductor package having semiconductor chip within central aperture of substrate.

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177. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.

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178. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.

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179. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package including stacked chips with aligned input/output pads.

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180. Thomas P. Glenn ; Lee J. Smith ; David A. Zoba ; Kambhampati Ramakrishna ; Vincent DiCaprio, Semiconductor package including stacked semiconductor dies and bond wires.

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181. Shim, Il Kwon; Ramakrishna, Kambhampati; DiCaprio, Vincent, Semiconductor package with spacer strips.

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182. Heo,Byong II, Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die.

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183. Haba, Belgacem, Semiconductor stacked die devices.

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184. Haba,Belgacem, Semiconductor stacked die devices and methods of forming semiconductor stacked die devices.

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185. Kirby, Kyle K.; Parekh, Kunal R., Semiconductor substrates with unitary vias and via terminals, and associated systems and methods.

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186. Kirby, Kyle K.; Parekh, Kunal R., Semiconductor substrates with unitary vias and via terminals, and associated systems and methods.

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187. Kirby, Kyle K.; Parekh, Kunal R., Semiconductor substrates with unitary vias and via terminals, and associated systems and methods.

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188. Kirby, Kyle K.; Parekh, Kunal R., Semiconductor substrates with unitary vias and via terminals, and associated systems and methods.

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189. Chong, John; Lee, Seung Bok; MacDonald, Noel; Lewis, Robert; Hunt, Peter, Shaped electrodes for micro-electro-mechanical-system (MEMS) devices to improve actuator performance and methods for fabricating the same.

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190. Ahn, Kie Y.; Forbes, Leonard, Silicon interposer with optical connections.

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191. Kie Y. Ahn ; Leonard Forbes, Silicon interposer with optical connections.

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192. Anderson, Brent A.; Andry, Paul S.; Sprogis, Edmund J.; Tsang, Cornelia K., Silicon-on-insulator structures for through via in silicon carriers.

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193. Kelly C. Casey ; Elmer Lee Turner, Jr., Single side contacts for a semiconductor device.

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194. Avsian, Osher; Grinman, Andrey; Humpston, Giles; Margalit, Moti, Stack packages using reconstituted wafers.

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195. Ozguz, Volkan; Pepe, Angel; Yamaguchi, James; Boyd, W. Eric; Albert, Douglas; Camien, Andrew, Stackable semiconductor chip layer comprising prefabricated trench interconnect vias.

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196. Shin,WonSun; Chun,DoSung; Lee,SangHo; Lee,SeonGoo; DiCaprio,Vincent, Stackable semiconductor package having semiconductor chip within central through hole of substrate.

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197. Haba, Belgacem; Mohammed, Ilyas, Stacked assembly including plurality of stacked microelectronic elements.

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198. Ahn Kie Y. ; Forbes Leonard, Stacked integrated circuits.

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199. Ahn Kie Y. ; Forbes Leonard, Stacked integrated circuits.

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200. Kie Y. Ahn ; Leonard Forbes, Stacked integrated circuits.

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201. Kriman, Moshe; Avsian, Osher; Haba, Belgacem; Humpston, Giles; Burshtyn, Dmitri, Stacked microelectronic assemblies having vias extending through bond pads.

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202. Maley Reading G., Stacked multi-chip modules using C4 interconnect technology having improved thermal management.

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203. Jeong,Se Young; Lee,Kang Wook, Stacked multi-chip semiconductor package improving connection reliability of stacked chips.

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204. Ahn Kie Y. ; Forbes Leonard ; Cloud Eugene H., Structure and method for a high performance electronic packaging assembly.

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205. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Structure and method for a high-performance electronic packaging assembly.

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206. Geusic Joseph E. ; Forbes Leonard ; Ahn Kie Y., Structure and method for an electronic assembly.

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207. Joseph E. Geusic ; Leonard Forbes ; Kie Y. Ahn, Structure and method for an electronic assembly.

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208. Rollin, Jean-Marc; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken; Oliver, J. Marcus; Smith, Tim, Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.

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209. Uzoh, Cyprian Emeka; Monadgemi, Pezhman; Caskey, Terrence; Ayatollahi, Fatima Lina; Haba, Belgacem; Woychik, Charles G.; Newman, Michael, Structures for heat dissipating interposers.

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210. Hovey, Ian; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken, Substrate-free interconnected electronic mechanical structural systems.

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211. Hovey, Ian; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken, Substrate-free interconnected electronic mechanical structural systems.

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212. Hovey, Ian; Reid, J. Robert; Sherrer, David; Stacy, Will; Vanhille, Ken, Substrate-free mechanical interconnection of electronic sub-systems using a spring configuration.

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213. Farnworth Warren M., Surface mount IC using silicon vias in an area array format or same size as die array.

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214. Farnworth Warren M., Surface mount IC using silicon vias in an area array format or same size as die array.

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215. Warren M. Farnworth, Surface mount ic using silicon vias in an area array format or same size as die array.

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216. Vanhille, Kenneth; Sherrer, David, Thermal management.

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217. Shin,Won Sun; Chun,Do Sung; Lee,Seon Goo; Shim,Il Kwon; DiCaprio,Vincent, Thin semiconductor package including stacked dies.

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218. Kong, Sik On, Three dimensional IC package module.

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219. Kong, Sik On, Three dimensional IC package module.

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220. Sik On Kong SG, Three dimensional IC package module.

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221. Wu,Weng Jin; Chiou,Wen Chih, Three dimensional integrated circuit and method of making the same.

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222. Pogge,H. Bernhard; Yu,Roy, Three-dimensional device fabrication method.

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223. Houck, William D.; Sherrer, David W., Three-dimensional microstructure having a first dielectric element and a second multi-layer metal element configured to define a non-solid volume.

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224. Houck, William D.; Sherrer, David W., Three-dimensional microstructures having a re-entrant shape aperture and methods of formation.

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225. Huang, Min Lung; Wang, Wei Chung; Cheng, Po Jen; Yee, Kuo Chung; Su, Ching Huei; Lo, Jian Wen; Lin, Chian Chi, Three-dimensional package and method of making the same.

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226. Huang, Min-Lung; Wang, Wei-Chung; Cheng, Po-Jen; Yee, Kuo-Chung; Su, Ching-Huei; Lo, Jian-Wen; Lin, Chian-Chi, Three-dimensional package and method of making the same.

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227. Huang,Min Lung; Wang,Wei Chung; Cheng,Po Jen; Yee,Kuo Chung; Su,Ching Huei; Lo,Jian Wen; Lin,Chian Chi, Three-dimensional package and method of making the same.

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228. Nowak, Matthew Michael; Gu, Shiqun, Through silicon via with embedded decoupling capacitor.

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229. Nowak, Matthew Michael; Gu, Shiqun, Through substrate via with embedded decoupling capacitor.

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230. Casey, Kelly C., Thyristor circuit providing overcurrent protection to a low impedance load.

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231. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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232. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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233. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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234. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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235. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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236. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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237. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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238. Sherrer, David, Transition structure between a rectangular coaxial microstructure and a cylindrical coaxial cable using step changes in center conductors thereof.

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239. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.

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240. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.

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241. Haba, Belgacem; Mohammed, Ilyas; Mirkarimi, Laura; Kriman, Moshe, Wafer level edge stacking.

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242. Thomas P. Glenn ; Steven Webster ; Vincent DiCaprio, Wafer level production of chip size semiconductor packages.

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243. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode and wafer-level light emitting diode package.

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244. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode package and method of fabricating the same.

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245. Seo, Won Cheol; Cho, Dae Sung, Wafer-level light emitting diode package and method of fabricating the same.

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246. Vanhille, Kenneth; Sherrer, David, Waveguide balun having waveguide structures disposed over a ground plane and having probes located in channels.

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247. Park, Young Kuk; Han, Byung Joon; Kim, Jae Dong, Wire bonding method and semiconductor package manufactured using the same.

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248. Park, Young Kuk; Han, Byung Joon; Kim, Jae Dong, Wire bonding method for a semiconductor package.

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249. Ahn, Kie Y.; Forbes, Leonard, Wireless communications system and method of making.

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250. Ahn, Kie Y.; Forbes, Leonard, Wireless communications system employing a chip carrier.

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