초록 ▼

A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will dischar

A test circuit and method for a semiconductor memory array such as a dynamic random access memory (DRAM) or static random access memory (SRAM) array that reduces the required testing time. A row of memory cells is concurrently written to a logic level, then read. Any faulty memory cells will discharge both true and complementary data lines through a diode or a diode-connected FET. The resulting voltage on the data line is less than its precharged high logic level, allowing detection of any faulty memory cell in the row of memory cells.

대표청구항 ▼

A semiconductor memory, comprising: a plurality of memory cells, each memory cell addressable by a row address and a column address; a plurality of word lines providing row addressing to the plurality of memory cells; a plurality of bit lines providing column addressing to the plurality of memory ce

A semiconductor memory, comprising: a plurality of memory cells, each memory cell addressable by a row address and a column address; a plurality of word lines providing row addressing to the plurality of memory cells; a plurality of bit lines providing column addressing to the plurality of memory cells; and a data bus comprising a plurality of data lines, wherein each data line is coupled to the plurality of bit lines through a plurality of bit line access field-effect transistors (FETs), and wherein each data line is coupled to the plurality of bit lines through a plurality of bit line test devices, each bit line test device having a unidirectional conduction property.