[특허]Methods and etchants for etching oxides of silicon with low selectivity in a vapor phase system

[미국특허] Methods and etchants for etching oxides of silicon with low selectivity in a vapor phase system 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/311
출원번호	US-0601787 (1996-02-15)
발명자 / 주소	Torek Kevin James (Boise ID) Lee Whonchee (Boise ID) Hawthorne deceased Richard C. (late of Nampa ID)
출원인 / 주소	Micron Technology, Inc. (Boise ID 02)
인용정보	피인용 횟수 : 32 인용 특허 : 8

초록 ▼

A surface having exposed doped silicon dioxide such as BPSG is cleaned with a vapor phase solution that etches thermal oxide at least one-third as fast as it etches the exposed doped silicon dioxide, resulting in more thorough cleaning with less removal of the exposed doped silicon dioxide. Specific applications to formation of container capacitors are disclosed. Preferred cleaning vapor phase solutions include about 1% water, about 5% hydrogen fluoride, and about 5% ammonia. The vapor phase solution is also useful in cleaning methods in which a refractory metal silicide is exposed to the cleaning vapor phase solution such as in cleaning prior to spacer formation or prior to a gate stack contact fill, in which case about 500 PPMV water, about 2% hydrogen fluoride, and about 2% ammonia is most preferred.

대표청구항 ▼

A method for cleaning a surface having exposed doped silicon dioxide, said method comprising: forming a surface situated on a semiconductor substrate., said surface having exposed doped silicon dioxide; and cleaning said surface with said exposed doped silicon dioxide in a vapor phase solution comprising in the range of about 0.01 to 104 PPMV initiator gas, about 103 to 2×105 PPMV hydrogen fluoride, and about 103 to 2×105 PPMV ammonia, wherein said vapor phase solution etches thermal oxide at least one-half the rate at which said vapor phase solution etches said doped silicon dioxide.

이 특허에 인용된 특허 (8) 인용/피인용 타임라인 분석

Barnes Michael S. (San Francisco CA) Keller John H. (Poughkeepsie NY) Holber William M. (Boston MA) Cotler Tina J. (Newburgh NY) Chapple-Sokol Jonathan D. (Poughkeepsie NY) Podlesnik Dragan (New York, Etching of silicon dioxide selectively to silicon nitride and polysilicon.
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Izumi Akira (Kyoto JPX) Toei Keiji (Kyoto JPX) Watanabe Nobuatsu (Kyoto JPX) Chong Yong-Bo (Kyoto JPX), Method for removing a film on a silicon layer surface.
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Man Yong (Dallas TX), Method for selectively etching oxides.
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Tanaka Masato (Shiga JPX), Method for selectively removing an insulating film.
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Nishino Hirotaka (Yokohama JPX) Hayasaka Nobuo (Yokohama JPX) Okano Haruo (Tokyo JPX), Method of oxide etching with condensed plasma reaction product.
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Beinvogl, Willy; Hasler, Barbara, Method of producing polysilicon structure in the 1 .mu.m range on substrates containing integrated semiconductor circuits by plasma etching.
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Izumi Akira (Kyoto JPX) Matsuka Takeshi (Kyoto JPX), Method of removing native oxide film from a contact hole on silicon wafer.
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Cathey David A. (Boise ID), Process for etching a multi-layer substrate.
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이 특허를 인용한 특허 (32) 인용/피인용 타임라인 분석

Willis, Stephen L., Chemical mechanical planarization of conductive material.
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Willis,Stephen L., Chemical mechanical planarization of conductive material.
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Lee, Whonchee; Pan, Pai; Gilton, Terry, Compositions for etching silicon with high selectivity to oxides and methods of using same.
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Whonchee Lee ; Pai Pan ; Terry Gilton, Compositions for etching silicon with high selectivity to oxides and methods of using same.
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Racanelli,Marco; Hu,Chun; Sherman,Phil N., Double-implant high performance varactor and method for manufacturing same.
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Agarwal Vishnu K., Electrode and capacitor structure for a semiconductor device and associated methods of manufacture.
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Gonzales David B. ; Bartlett Aaron T., Endpoint stabilization for polishing process.
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Gonzales, David B.; Bartlett, Aaron T., Endpoint stabilization for polishing process.
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Ko,Kei Yu, Etchant gas composition.
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Ko,Kei Yu, Etching methods.
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Cantell, Marc W.; Natzle, Wesley; Ruegsegger, Steven M., Etching of hard masks.
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Ko,Kei Yu, Gas compositions.
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Ko, Kei-Yu, Gate stack structure.
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Kang,Inkuk; Kinoshita,Hiroyuki; Gabriel,Calvin T., Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure.
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Michael J. Danese, Method for treating an object using ultra-violet light.
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Kei-Yu Ko, Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher.
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Ko Kei-Yu, Method of etching doped silicon dioxide with selectivity to undoped silicon dioxide with a high density plasma etcher.
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Torek, Kevin J., Method of forming an inset in a tungsten silicide layer in a transistor gate stack.
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Torek,Kevin; Shea,Kevin; Graettinger,Thomas, Method of forming high aspect ratio structures.
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Torek Kevin J., Method of making an oxide structure having a finely calibrated thickness.
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Ieong,Meikei; Dokumaci,Omer H.; Kanarsky,Thomas S.; Ku,Victor, Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS.
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May Charles ; Cheung Robin, Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water.
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Nishimura,Eiichi; Iwasaki,Kenya, Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device.
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Criscuolo, Robert William; Pearce, Charles Walter, Oxide etch.
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Kevin J. Torek, Oxide structure having a finely calibrated thickness.
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Ramachandran, Ravikumar; Natzle, Wesley; Gutsche, Martin; Akatsu, Hiroyuki; Yu, Chien, Removal of post-rie polymer on A1/CU metal line.
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Torek Kevin James ; Lee Whonchee ; Hawthorne Richard C., Selective etching of oxides.
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Kimura Hiroshi,JPX, Semiconductor device comprising a contact hole of varying width thru multiple insulating layers.
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Torek,Kevin; Shea,Kevin, Semiconductor fabrication that includes surface tension control.
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Kei-Yu Ko, Semiconductor structure having a plurality of gate stacks.
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Ko, Kei-Yu, Undoped silicon dioxide as etch mask for patterning of doped silicon dioxide.
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Ko, Kei-Yu, Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Methods and etchants for etching oxides of silicon with low selectivity in a vapor phase system 원문보기