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Dual damascene with a protective mask for via etching 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/28
출원번호 US-0478324 (1995-06-07)
발명자 / 주소
  • Avanzino Steven (Cupertino CA) Gupta Subhash (San Jose CA) Klein Rich (Mountain View CA) Luning Scott D. (Menlo Park CA) Lin Ming-Ren (Cupertino CA)
출원인 / 주소
  • Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보 피인용 횟수 : 54  인용 특허 : 7

초록

A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used t

대표청구항

A method of fabricating interconnecting conductive lines and conductive vias in a layer of insulating material of a sufficient thickness to contain both the conductive lines and vias comprising the steps of: forming a conductive line opening with sidewalls and a bottom in a layer of insulating mater

이 특허에 인용된 특허 (7)

  1. Greco Stephen E. (LaGrangeville NY) Srikrishnan Kris V. (Wappingers Falls NY), Chip interconnection having a breathable etch stop layer.
  2. Andreshak Joseph C. (Mahopac NY) Baseman Robert J. (Brewster NY), Laser ablation damascene process.
  3. Chung In S. (Ichonkun KRX) Kim Youn J. (Bundangku KRX), Method for making a contact hole of a semiconductor device.
  4. Yoon Soo-Sik (Kyoungki-do KRX) Kim Jin-Woong (Seoul KRX) Oh Jin-Seung (Seoul KRX) Kim Il-Wook (Seoul KRX) Park Hee-Kook (Seoul KRX), Method for manufacturing a contact hole of a semiconductor device.
  5. Mattox Robert J. (Tempe AZ) Robinson Frederick J. (Scottsdale AZ), Method for obtaining submicron features from optical lithography technology.
  6. Cote William J. (Poughquag NY) Lee Pei-Ing P. (Williston VT) Sandwick Thomas E. (Hopewell Junction NY) Vollmer Bernd M. (Wappingers Falls NY) Vynorius Victor (Pleasant Valley NY) Wolff Stuart H. (Tul, Refractory metal capped low resistivity metal conductor lines and vias.
  7. Crotti Pier L. (Landriano ITX) Iazzi Nadia (Cremona ITX), Tapering of holes through dielectric layers for forming contacts in integrated devices.

이 특허를 인용한 특허 (54)

  1. Subramanian Ramkumar ; Singh Bhanwar ; Chan Simon ; Wang Fei, Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication.
  2. Akinmade-Yusuff, Hakeem B. S.; Choi, Samuel Sung Shik; Engbrecht, Edward R.; Fitzsimmons, John A., Bilayer trench first hardmask structure and process for reduced defectivity.
  3. Singh Bhanwar ; Templeton Michael K. ; Rangarajan Bharath ; Lyons Christopher F. ; Yedur Sanjay K. ; Subramanian Ramkumar, CVD plasma process to fill contact hole in damascene process.
  4. Singh, Bhanwar; Templeton, Michael K.; Rangarajan, Bharath; Lyons, Christopher F.; Yedur, Sanjay K.; Subramanian, Ramkumar, CVD plasma process to fill contact hole in damascene process.
  5. Omura Masayoshi,JPX, Damascene wiring with flat surface.
  6. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Dual damascene patterned conductor layer formation method.
  7. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX, Dual damascene patterned conductor layer formation method without etch stop layer.
  8. Yu Chen-Hua Douglas,TWX ; Jang Syun Ming,TWX, Dual damascene patterned conductor layer formation method without etch stop layer.
  9. Chen Chao-Cheng,TWX ; Lui Ming-Huei,TWX ; Liu Jen-Cheng,TWX ; Chao Li-chih,TWX ; Tsai Chia-Shiung,TWX, Dual damascene process for carbon-based low-K materials.
  10. Grassmann Andreas,DEX, Etching of contact holes.
  11. Lee Tze-Liang,TWX, Fabrication process for copper structures.
  12. Drynan John Mark,JPX, Formation method of contact/ through hole.
  13. Gurtej S. Sandhu ; Shubneesh Batra, Laser ablative removal of photoresist.
  14. Sandhu Gurtej S. ; Batra Shubneesh, Laser ablative removal of photoresist.
  15. Azuma Tsukasa,JPX ; Sato Takashi,JPX, Lithography process using one or more anti-reflective coating films and fabrication process using the lithography process.
  16. Nguyen Tue ; Hsu Sheng Teng, Low resistance contact between integrated circuit metal levels and method for same.
  17. Cao Min ; Theil Jeremy A ; Ray Gary W ; Vook Dietrich W, Method and apparatus for a dual-inlaid damascene contact to sensor.
  18. Lukanc Todd P. ; Brown Dirk ; Nogami Takeshi, Method for fabricating protected copper metallization.
  19. Chine-Gie Lou TW, Method for forming a via and interconnect in dual damascene.
  20. Lee Won-Jun,KRX, Method for forming an interconnection in a semiconductor device.
  21. Tao Hun-Jan,TWX ; Chen Chao-Cheng,TWX ; Tsai Chia-Shiung,TWX, Method of dual damascene etching.
  22. Kazuhide Abe JP, Method of embedding contact hole by damascene method.
  23. Hsu Shou-Yi,TWX ; Lui Hon-Hung,TWX ; Chuang Kun-Jung,TWX, Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes.
  24. Chen, Sheng-Hsiung; Tsai, Ming-Hsing, Method of forming dual damascene structure.
  25. Omura Masayoshi,JPX, Method of forming flat wiring layer.
  26. Guo, Xiaobo, Method of forming patterned film on a bottom and a top-surface of a deep trench.
  27. Podlesnik, Dragan; Lill, Thorsten; Chinn, Jeff; Pan, Shaoher X.; Khan, Anisul; Li, Maocheng; Wang, Yiqiong, Method of micromachining a multi-part cavity.
  28. Huang Yimin,TWX ; Yew Tri-Rung,TWX, Method to fabricate a dual metal-damascene structure in a substrate.
  29. Li Jianxun,SGX ; Chooi Simon,SGX ; Zhou Mei-Sheng,SGX, Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion.
  30. Stamper Anthony K., Methods for forming metal interconnects.
  31. Givens, John H.; Jost, Mark E., Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  32. Jeong Gi-Tae,KRX, Methods of fabricating conductive lines in integrated circuits using insulating sidewall spacers and conductive lines so fabricated.
  33. Yoo Bong-Young,KRX ; Choi Si-Young,KRX, Methods of forming electrical interconnects on semiconductor substrates.
  34. Lee, Sang woo; Choi, Gil heyun; Kang, Sang bom; Lee, Jong myeong; Park, Jin ho, Methods of forming metal wiring in semiconductor devices using etch stop layers.
  35. Lin Kang-Cheng,TWX, Modified dual damascene process.
  36. Dai Chang-Ming,TWX, Opposed two-layered photoresist process for dual damascene patterning.
  37. Chia-Shiun Tsai TW; Chao-Cheng Chen TW; Hun-Jan Tao TW, Plasma etch method for forming patterned oxygen containing plasma etchable layer.
  38. Michael S. Nashner ; Bruce Beattie, Post etch clean sequence for making a semiconductor device.
  39. Lee, Wai Mun, Remover compositions for dual damascene system.
  40. Lin Cheng-Tung,TWX ; Lee Yu-Hua,TWX ; Huang Jenn Ming,TWX ; Wu Cheng-Ming,TWX, Robust dual damascene process.
  41. Muto Yoshio,JPX, Semiconductor device and process of producing same.
  42. Yamamoto, Koji, Semiconductor device having a dual damascene interconnect structure and method for manufacturing same.
  43. Park, Byung-Jun; Hwang, Yoo-Sang, Semiconductor device having a self-aligned contact structure and methods of forming the same.
  44. Sandhu Gurtej S. ; Batra Shubneesh, Semiconductor processing method of forming openings in a material.
  45. Sandhu Gurtej S. ; Batra Shubneesh, Semiconductor processing methods of forming openings to devices and substrates, exposing material from which photoresist cannot be substantially selectively removed.
  46. Bass William Scott, Spacer - defined dual damascene process method.
  47. Koh Leong Tee,MYX ; Sajan Marokkey Raphael,SGX ; Cheng Tsun-Lung Alex,SGX ; Xie Joseph Zhifeng,SGX, Tri-layer resist method for dual damascene process.
  48. Dai Chang-Ming,TWX ; Huang Jammy Chin-Ming,TWX, Two-layered TSI process for dual damascene patterning.
  49. Lui,Lawrence; Tsai,Chia Shia; Chen,Chao Cheng; Liu,Jen Cheng, Underlayer protection for the dual damascene etching.
  50. Kennedy, Joseph Travis; Chung, Henry; George, Anna, Use of sacrificial inorganic dielectrics for dual damascene processes utilizing organic intermetal dielectrics.
  51. Givens, John H.; Jost, Mark E., Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  52. Givens, John H.; Jost, Mark E., Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  53. John H. Givens ; Mark E. Jost, Utilization of disappearing silicon hard mask for fabrication of semiconductor structures.
  54. Andrew Lu ; Juan Alexander Chediak, Via masked line first dual damascene.
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