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Fan-out semiconductor chip assembly 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/60
출원번호 US-0653016 (1996-05-24)
발명자 / 주소
  • DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA) Faraci Tony (Georgetown TX)
출원인 / 주소
  • Tessera, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 161  인용 특허 : 38

초록

A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid materi

대표청구항

A method of making a semiconductor chip assembly comprising the steps of: (a) providing a subassembly including a semiconductor chip having a front surface and having contacts on the front surface, and a package element attached to the chip so that a peripheral region of the package element projects

이 특허에 인용된 특허 (38)

  1. Reylek Robert S. (Shoreview MN) Berg James G. (North St. Paul MN), Anisotropically conductive polymeric matrix.
  2. Grabbe Dimitry G. (Middletown PA), Area array connector.
  3. Matunami Mituo (Izumisano JA), Beam lead formation method.
  4. Nakanishi Keiichirou (Kokubunji JPX) Yamada Minoru (Hanno JPX) Yamamoto Masakazu (Kodaira JPX) Ogihara Satoru (Hitachi JPX) Shinohara Hiroichi (Hitachi JPX) Suzuki Hideo (Katsuta JPX), Chip carrier.
  5. Matsumoto Kunio (Yokohama JPX) Oshima Muneo (Yokohama JPX) Sakaguchi Suguru (Chigasaki JPX), Connecting structure for electronic part and method of manufacturing the same.
  6. Noro Takanobu (Yokohama JPX) Matsumoto Kunio (Yokohama JPX) Oshima Muneo (Yokohama JPX) Kanda Naoya (Yokohama JPX) Sakaguchi Suguru (Yokohama JPX) Murata Akira (Tokyo JPX), Connecting structure of electronic part and electronic device using the structure.
  7. Yoshizawa Tetsuo (Yokohama) Tarayama Yoshimi (Odawara) Kondo Hiroshi (Yokohama) Sakaki Takashi (Tokyo) Haga Shunichi (Yokohama) Ichida Yasuteru (Machida) Konishi Masaki (Ebina JPX), Electric circuit device having an electric connecting member and electric circuit components.
  8. Zifcak Mark S. (Putnam CT) Kosa Bruce G. (Woodstock CT), Electrical circuit board interconnect.
  9. Grabbe Dimitry G. (Middletown PA) Korsunsky Iosif (Harrisburg PA), Electrical socket.
  10. Jacobs Scott L. (Apex NC), Extended integration semiconductor structure with wiring layers.
  11. Grabbe Dimitry G. (Middletown PA), Field emitter array integrated circuit chip interconnection.
  12. Carey David H. (Austin TX), Flip substrate for chip mount.
  13. Ludden Michael J. (Swindon TX GB2) Nyholm Peter (Austin TX), Hybrid microchip bonding article.
  14. Tanizawa Tetsu (Kawasaki JPX), Integrated circuit semiconductor device formed on a wafer.
  15. Carlommagno William D. (Redwood City CA) Cummings Dennis E. (Placerville CA) Gliga Alexandru S. (San Jose CA), Interconnection of electronic components.
  16. Mallik Debendra (Chandler AZ) Bhattacharyya Bidyut K. (Chandler AZ), Lead grid array integrated circuit.
  17. McShane Michael B. (Austin TX), Low cost integrated circuit bonding process.
  18. Flammer Wieland (Cleebronn DEX) Weber Roland (Heilbronn-Bockingen DEX) Weiher Gerhard (Brackenheim DEX) Troner Jakob (Heilbronn-Bockingen DEX), Method for contacting contact areas located on semiconductor bodies.
  19. Sado Ryoichi (Saitama JPX) Tahara Kazutoki (Saitama JPX), Method for manufacturing an elastic composite body with metal wires embedded therein.
  20. Ho Chung W. (Monte Sereno CA) Min B. Y. (Cupertino CA), Method of forming a multilevel interconnection device.
  21. Jacobs Scott L. (Apex NC), Method of making a extended integration semiconductor structure.
  22. Rose Ren (Bretonneux FRX), Method of making an electronic module, for insertion into an electronic memory-card body.
  23. DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA), Microelectronic mounting with multiple lead deformation and bonding.
  24. DiStefano Thomas H. (Monte Sereno CA) Smith ; Jr. John W. (Austin TX), Microelectronics unit mounting with multiple lead bonding.
  25. Samuels George J. (Syracuse NY), Novel nickel/indium/other metal alloy for use in the manufacture of electrical contact areas of electrical devices.
  26. Yamazaki Shunpei (Tokyo JPX) Hayashi Shigenori (Atsugi JPX), Plasma-assisted CVD of carbonaceous films by using a bias voltage.
  27. Phy William S. (Los Altos Hills CA), Process of forming a compliant lead frame for array-type semiconductor packages.
  28. Oettel Friedrich H. (Daytona Beach FL), Pyroelectric detector.
  29. Khandros Igor Y. (Peekskill NY) DiStefano Thomas H. (Bronxville NY), Semiconductor chip assemblies and methods of making same.
  30. Lee James C. K. (Los Altos CA) Amdahl Gene M. (Atherton CA) Beck Richard L. (Cupertino CA) Quinn Robert F. (Cupertino CA) Sochor Jerzy R. (San Jose CA), Semiconductor chip interface.
  31. Ueda Tetsuya (Itami JPX), Semiconductor device.
  32. Otsuka Kanji (Higashiyamato JPX) Kato Masao (Hadano JPX) Kumagai Takashi (Isehara JPX) Usami Mitsuo (Ohme JPX) Kuroda Shigeo (Ohme JPX) Sahara Kunizo (Nishitama JPX) Yamada Takeo (Koganei JPX) Miyamo, Semiconductor device having leads for mounting to a surface of a printed circuit board.
  33. Cain Earl S. (Napa CA), Semiconductor die packages having lead support frame.
  34. Walters Peter E. (London GB2) Williams Anthony M. (Iver GB2), Sensing apparatus.
  35. Marks Robert (South Burlington VT) Phelps ; Jr. Douglas W. (Burlington VT) Ward William C. (Burlington VT), Substrate with multiple type connections.
  36. Grabbe Dimitry G. (Middletown PA) Korsunsky Iosif (Harrisburg PA) Ringler Daniel R. (Elizabethville PA), Surface mount electrical connector.
  37. Bobb Lloyd C. (Warminster PA) Krumboltz Howard D. (Chalfont PA), Thermal phase modulator and method of modulation of light beams by optical means.
  38. Malladi Deviprasad (Campbell CA) Bogatin Eric L. (San Jose CA) Zand Bahram (Laguna Niguel CA), Thin film chip capacitor for electrical noise reduction in integrated circuits.

이 특허를 인용한 특허 (161)

  1. Caskey, Terrence; Mohammed, Ilyas; Uzoh, Cyprian Emeka; Woychik, Charles G.; Newman, Michael; Monadgemi, Pezhman; Co, Reynaldo; Chau, Ellis; Haba, Belgacem, BVA interposer.
  2. Burtzlaff,Robert; Haba,Belgacem; Humpston,Giles; Tuckerman,David B.; Warner,Michael; Mitchell,Craig S., Back-face and edge interconnects for lidded package.
  3. Subido, Willmar; Co, Reynaldo; Zohni, Wael; Prabhu, Ashok S., Ball bonding metal wire bond wires to metal pads.
  4. Leonard E. Mess, Ball grid array (BGA) encapsulation mold.
  5. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  6. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  7. Mess Leonard E., Ball grid array (BGA) encapsulation mold.
  8. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.
  9. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.
  10. Haba, Belgacem; Mohammed, Ilyas; Wang, Liang, Batch process fabrication of package-on-package microelectronic assemblies.
  11. Katkar, Rajesh; Gao, Guilian; Woychik, Charles G.; Zohni, Wael, Bond via array for thermal conductivity.
  12. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Chip package.
  13. Thomas H. DiStefano ; John W. Smith, Chip with internal signal routing in external element.
  14. Thomas H. Distefano, Compliant semiconductor chip package with fan-out leads and method of making same.
  15. Belgacem Haba, Conductive leads with non-wettable surfaces.
  16. Xie,Yuanlin, Consolidated flip chip BGA assembly process and apparatus.
  17. Uzoh, Cyprian Emeka; Katkar, Rajesh, Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects.
  18. DeLaCruz, Javier A.; Awujoola, Abiola; Prabhu, Ashok S.; Lattin, Christopher W.; Sun, Zhuowen, Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces.
  19. Mess, Leonard E., Encapsulation method in a molding machine for an electronic device.
  20. Haba, Belgacem; Mohammed, Ilyas, Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation.
  21. Katkar, Rajesh, Fine pitch BVA using reconstituted wafer with area array accessible for testing.
  22. Katkar, Rajesh, Fine pitch BVA using reconstituted wafer with area array accessible for testing.
  23. Smith John W. ; Haba Belgacem, Flexible lead structures and methods of making same.
  24. Smith, John W.; Haba, Belgacem, Flexible lead structures and methods of making same.
  25. Mohammed, Ilyas; Beroz, Masud, Heat spreading substrate with embedded interconnects.
  26. Beroz,Masud; Warner,Michael; Smith,Lee; Urbish,Glenn; Kang,Teck Gyu; Park,Jae M.; Kubota,Yoichi, High frequency chip packages with connecting elements.
  27. Warner, Michael, High-frequency chip packages.
  28. Warner, Michael, High-frequency chip packages.
  29. Warner,Michael; Smith,Lee; Haba,Belgacem; Urbish,Glenn; Beroz,Masud; Kang,Teck Gyu, High-frequency chip packages.
  30. Katkar, Rajesh; Uzoh, Cyprian Emeka, Low CTE component with wire bond interconnects.
  31. Katkar, Rajesh; Uzoh, Cyprian Emeka, Low CTE component with wire bond interconnects.
  32. Smith, John W., Low cost and compliant microelectronic packages for high I/O and fine pitch.
  33. Smith, John W., Low cost and compliant microelectronic packages for high i/o and fine pitch.
  34. Haba, Belgacem; Kubota, Yoichi, Manufacture of mountable capped chips.
  35. Leu, Felix, Method and apparatus for mounting semiconductor chips.
  36. Kwang, Chua Swee; Poo, Chia Yong, Method for fabricating semiconductor packages with discrete components.
  37. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Method for making a microelectronic assembly having conductive elements.
  38. Co, Reynaldo; Mirkarimi, Laura, Method for package-on-package assembly with wire bonds to encapsulation surface.
  39. Co, Reynaldo; Mirkarimi, Laura, Method for package-on-package assembly with wire bonds to encapsulation surface.
  40. Smith John W. ; Fjelstad Joseph, Method of fabricating a microelectronic assembly using sheets with gaps to define lead regions.
  41. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Method of fabricating chip package.
  42. DiStefano,Thomas H., Method of fabricating semiconductor chip assemblies.
  43. DiStefano,Thomas H., Method of fabricating semiconductor chip assemblies.
  44. Thomas H. DiStefano, Method of fabricating semiconductor chip assemblies.
  45. Zhao, Zhijun; Alatorre, Roseann, Method of forming a component having wire bonds and a stiffening layer.
  46. Mohammed, Ilyas, Method of forming a wire bond having a free end.
  47. DiStefano Thomas H. ; Smith John W. ; Mitchell Craig, Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures.
  48. Thomas H. Distefano ; John W. Smith ; Craig Mitchell, Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures.
  49. Shiro Ozaki JP; Kenji Edazawa JP; Kazuhiro Sugiyama JP, Method of manufacturing bonded structure of film substrate and semiconductor chip.
  50. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  51. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  52. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  53. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  54. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  55. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  56. Zilber, Gil; Katraro, Reuven; Aksenton, Julia; Oganesian, Vage, Methods and apparatus for packaging integrated circuit devices.
  57. Zilber,Gil; Aksenton,Julia; Oganesian,Vage, Methods and apparatus for packaging integrated circuit devices.
  58. Zilber,Gil; Aksenton,Julia; Oganesian,Vage, Methods and apparatus for packaging integrated circuit devices.
  59. Zilber,Gil; Katraro,Reuven; Aksenton,Julia; Oganesian,Vage, Methods and apparatus for packaging integrated circuit devices.
  60. Leonard E. Mess, Methods for ball grid array (BGA) encapsulation mold.
  61. Distefano Thomas H. ; Mitchell Craig S., Methods of encapsulating a semiconductor chip using a settable encapsulant.
  62. Distefano Thomas H. ; Mitchell Craig S., Methods of encapsulating a semiconductor chip using a settable encapsulant.
  63. Thomas H. Distefano ; Craig S. Mitchell, Methods of encapsulating a semiconductor chip using a settable encapsulant.
  64. Smith,John W., Methods of making microelectronic packages.
  65. Warner,Michael; Beroz,Masud; Light,David; Li,Delin; Castillo,Dennis; Wang,Hung ming; Smith,John W., Microelectronic assemblies having low profile connections.
  66. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation.
  67. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation.
  68. Warner,Michael; Haba,Belgacem; Beroz,Masud, Microelectronic assemblies incorporating inductors.
  69. Mohammed, Ilyas; Haba, Belgacem, Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation.
  70. Smith John W. ; Fjelstad Joseph, Microelectronic assembly fabrication with terminal formation from a conductive layer.
  71. Smith John W. ; Fjelstad Joseph, Microelectronic assembly fabrication with terminal formation from a conductive layer.
  72. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface.
  73. Light, David, Microelectronic assembly formation with lead displacement.
  74. Smith, John W.; Koblis, Mitchell, Microelectronic assembly formation with releasable leads.
  75. John W. Smith ; Joseph Fjelstad, Microelectronic assembly incorporating lead regions defined by gaps in a polymeric sheet.
  76. Nystrom, Michael J.; Humpston, Giles, Microelectronic assembly with multi-layer support structure.
  77. Nystrom, Michael J.; Humpston, Giles, Microelectronic assembly with multi-layer support structure.
  78. Haba, Belgacem; Crisp, Richard Dewitt; Zohni, Wael, Microelectronic element with bond elements to encapsulation surface.
  79. DiStefano Thomas H., Microelectronic mounting with multiple lead deformation using restraining straps.
  80. Distefano Thomas H., Microelectronic mounting with multiple lead deformation using restraining straps.
  81. Thomas H. DiStefano, Microelectronic mounting with multiple lead deformation using restraining straps.
  82. Prabhu, Ashok S.; Katkar, Rajesh, Microelectronic package for wafer-level chip scale packaging with fan-out.
  83. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.
  84. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.
  85. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.
  86. Haba, Belgacem, Microelectronic package with terminals on dielectric mass.
  87. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.
  88. Haba, Belgacem; Kang, Teck-Gyu; Mohammed, Ilyas; Chau, Ellis, Microelectronic packages and methods therefor.
  89. DiStefano,Thomas H., Microelectronic packages with elongated solder interconnections.
  90. Thomas H. DiStefano, Microelectronic packages with solder interconnections.
  91. Haba, Belgacem, Microelectronic packaging methods and components.
  92. Masud Beroz ; Joseph Fjelstad ; Belgacem Haba ; Christopher M. Pickett ; John Smith, Microelectronic unit forming methods and materials.
  93. Uzoh, Cyprian Emeka; Katkar, Rajesh, Multiple bond via arrays of different wire heights on a same substrate.
  94. Uzoh, Cyprian Emeka; Katkar, Rajesh, Multiple bond via arrays of different wire heights on a same substrate.
  95. Lin, Mou-Shiung; Peng, Bryan, Multiple chips bonded to packaging structure with low noise and multiple selectable functions.
  96. Haba, Belgacem; Co, Reynaldo; Cizek, Rizza Lee Saga; Zohni, Wael, Off substrate kinking of bond wire.
  97. Haba, Belgacem; Co, Reynaldo; Saga Cizek, Rizza Lee; Zohni, Wael, Off substrate kinking of bond wire.
  98. DiStefano, Thomas H.; Smith, John W., Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element.
  99. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  100. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  101. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  102. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  103. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young, Package-on-package assembly with wire bond vias.
  104. Chau, Ellis; Co, Reynaldo; Alatorre, Roseann; Damberg, Philip; Wang, Wei-Shun; Yang, Se Young; Zhao, Zhijun, Package-on-package assembly with wire bond vias.
  105. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  106. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  107. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  108. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  109. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  110. Sato, Hiroaki; Kang, Teck-Gyu; Haba, Belgacem; Osborn, Philip R.; Wang, Wei-Shun; Chau, Ellis; Mohammed, Ilyas; Masuda, Norihito; Sakuma, Kazuo; Hashimoto, Kiyoaki; Inetaro, Kurosawa; Kikuchi, Tomoyuki, Package-on-package assembly with wire bonds to encapsulation surface.
  111. Prabhu, Ashok S.; Katkar, Rajesh, Packaged microelectronic device for a package-on-package device.
  112. Haba, Belgacem; Mohammed, Ilyas, Pin attachment.
  113. Co, Reynaldo; Villavicencio, Grant; Zohni, Wael, Pressing of wire bond wire tips to provide bent-over tips.
  114. Mohammed, Ilyas, Reconstituted wafer-level package DRAM.
  115. Mohammed, Ilyas, Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package.
  116. Lin, Mou-Shiung; Chou, Chiu-Ming, Semiconductor chip and method for fabricating the same.
  117. Distefano Thomas H., Semiconductor chip package with expander ring and method of making same.
  118. Smith, John W.; Haba, Belgacem, Semiconductor chip package with interconnect structure.
  119. Smith, John W.; Haba, Belgacem, Semiconductor chip package with interconnect structure.
  120. Kwang, Chua Swee; Poo, Chia Yong, Semiconductor package having die with recess and discrete component embedded within the recess.
  121. Maruyama, Shigeyuki; Tashiro, Kazuhiro; Haseyama, Makoto, Semiconductor testing device.
  122. Maruyama, Shigeyuki; Tashiro, Kazuhiro; Haseyama, Makoto; Fukaya, Futoshi, Semiconductor testing device.
  123. Maruyama,Shigeyuki; Tashiro,Kazuhiro; Haseyama,Makoto, Semiconductor testing device.
  124. Honer, Kenneth Allen, Sequential fabrication of vertical conductive interconnects in capped chips.
  125. Haba, Belgacem; Co, Reynaldo; Saga Cizek, Rizza Lee; Zohni, Wael, Severing bond wire by kinking and twisting.
  126. Haba, Belgacem, Stackable molded microelectronic packages.
  127. Haba, Belgacem, Stackable molded microelectronic packages.
  128. Haba, Belgacem, Stackable molded microelectronic packages.
  129. Haba, Belgacem, Stackable molded microelectronic packages.
  130. Haba, Belgacem, Stackable molded microelectronic packages.
  131. Haba, Belgacem, Stackable molded microelectronic packages with area array unit connectors.
  132. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  133. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  134. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  135. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  136. Haba, Belgacem; Mitchell, Craig S.; Beroz, Masud, Stacked packaging improvements.
  137. Kwang, Chua Swee; Poo, Chia Yong, Stacked semiconductor package having discrete components.
  138. Villavicencio, Grant; Lee, Sangil; Alatorre, Roseann; Delacruz, Javier A.; McGrath, Scott, Stiffened wires for offset BVA.
  139. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  140. Lee, Jin-Yuan; Huang, Ching-Cheng; Lin, Mou-Shiung, Structure and manufacturing method of chip scale package.
  141. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Structure for microelectronic packaging with bond elements to encapsulation surface.
  142. Haba, Belgacem; Mohammed, Ilyas; Caskey, Terrence; Co, Reynaldo; Chau, Ellis, Structure for microelectronic packaging with bond elements to encapsulation surface.
  143. Haba, Belgacem; Mohammed, Ilyas, Structure for microelectronic packaging with terminals on dielectric mass.
  144. Lee, Jin-Yuan; Lin, Mou-Shiung, Structure of high performance combo chip and processing method.
  145. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.
  146. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.
  147. Mohammed, Ilyas, Substrate-less stackable package with wire-bond interconnect.
  148. East, W. Joe; Weiss, Elliot, Thermal transfer devices with fluid-porous thermally conductive core.
  149. Lepp, James Randolph Winter; Cormier, Jean-Philippe Paul; Schwandt, Sheldon Terry; Los, Oleg; Braun, Petra, UICC apparatus.
  150. Lepp, James Randolph Winter; Cormier, Jean-Philippe Paul; Schwandt, Sheldon Terry; Los, Oleg; Braun, Petra, UICC apparatus.
  151. Lepp, James Randolph Winter; Cormier, Jean-Philippe Paul; Schwandt, Sheldon Terry; Los, Oleg; Braun, Petra, UICC apparatus.
  152. Lepp, James Randolph Winter; Cormier, Jean-Philippe Paul; Schwandt, Sheldon Terry; Los, Oleg; Braun, Petra, UICC apparatus.
  153. Lepp, James Randolph Winter; Cormier, Jean-Philippe Paul; Schwandt, Sheldon Terry; Los, Oleg; Braun, Petra, UICC apparatus and related methods.
  154. Schwandt, Sheldon Terry; Dehmoubed, Farzin; Infanti, James Carl; Lepp, James Randolph Winter; Los, Oleg, Universal integrated circuit card apparatus and related methods.
  155. Katkar, Rajesh; Vu, Tu Tam; Lee, Bongsub; Bang, Kyong-Mo; Li, Xuan; Huynh, Long; Guevara, Gabriel Z.; Agrawal, Akash; Subido, Willmar; Mirkarimi, Laura Wills, Wafer-level packaging using wire bond wires in place of a redistribution layer.
  156. Co, Reynaldo; Zohni, Wael; Cizek, Rizza Lee Saga; Katkar, Rajesh, Wire bond support structure and microelectronic package including wire bonds therefrom.
  157. Co, Reynaldo; Zohni, Wael; Saga Cizek, Rizza Lee; Katkar, Rajesh, Wire bond support structure and microelectronic package including wire bonds therefrom.
  158. Awujoola, Abiola; Sun, Zhuowen; Zohni, Wael; Prabhu, Ashok S.; Subido, Willmar, Wire bond wires for interference shielding.
  159. Awujoola, Abiola; Sun, Zhuowen; Zohni, Wael; Prabhu, Ashok S.; Subido, Willmar, Wire bond wires for interference shielding.
  160. Huang, Shaowu; Delacruz, Javier A., Wire bonding method and apparatus for electromagnetic interference shielding.
  161. Prabhu, Ashok S.; Katkar, Rajesh, ‘RDL-First’ packaged microelectronic device for a package-on-package device.
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