초록 ▼

A memory element that includes a stored charge element coupled to a bi-directional voltage dropping element that exhibits substantially definite voltage drops when conducting in each direction is the basis for a family of memory cells and circuits. An extremely compact dynamic memory cell (200) capa

A memory element that includes a stored charge element coupled to a bi-directional voltage dropping element that exhibits substantially definite voltage drops when conducting in each direction is the basis for a family of memory cells and circuits. An extremely compact dynamic memory cell (200) capable of being stacked includes a capacitor (204) or any other suitable stored charge device, and a voltage dropping element such as a Zener diode (208), a pair of parallel, reverse-connected diodes (910, 920), or any other suitable voltage dropping device having substantially definite voltage drop thresholds when conducting in each direction. Another type of dynamic memory (1000) is read through a transistor (1020) to provide non-destructive reads. Another type of dynamic memory (1200) has column bit lines (1212) that are shared by adjacent cells having memory elements (1230, 1240). An SRAM cell (1300, 1400) is made of a latch (1310) that is accessed through a memory element (1320, 1420). A dynamic register (1500, 1700) is made from several stages (1510 and 1550, 1710 and 1750), each of which includes a master stage (1520, 1720) followed by a slave stage (1530, 1730). The master and slave stages contain memory elements. The various circuits are operated using suitable voltages and voltage sequences.

대표청구항 ▼

A memory comprising: a first stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a first charge input path having a second memory access node, the first charge input path being a charge path into the se

A memory comprising: a first stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a first charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur; and a first charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, the respective voltage drop thresholds of the first charge input path and the first charge output path being unequal; wherein at least one of the first, second and third memory access nodes is a bit node.