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Reverse damascene via structures 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0572317 (1995-12-14)
발명자 / 주소
  • Liu Yowjuang W. (San Jose CA) Chang Kuang-Yeh (Los Gatos CA)
출원인 / 주소
  • Advanced Micro Devices, Inc. (Sunnyvale CA 02)
인용정보 피인용 횟수 : 72  인용 특허 : 9

초록

A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in d

대표청구항

A method of manufacturing a semiconductor device, which method comprises: depositing a plurality of sequential dielectric and conductive layers on a semiconductor substrate, each conductive layer comprising at least one conductive pattern; and forming an interconnection electrically connecting a con

이 특허에 인용된 특허 (9)

  1. Andreshak Joseph C. (Mahopac NY) Baseman Robert J. (Brewster NY), Laser ablation damascene process.
  2. Manning Monte (Kuna ID), Method for forming a multilevel interconnect structure on a semiconductor wafer.
  3. Okumura Katsuya (Yokohama JPX), Method of manufacturing a semiconductor device having tapered pillars.
  4. Rhodes, Stephen J.; Oakley, Raymond E., Method of producing a layered structure.
  5. McMann Ronald E. (Rosenberg TX) Garcia ; Jr. Evaristo (Rosenberg TX) Welch Michael T. (Sugar Land TX) Thompson Stephen W. (Richmond TX), Planar metal interconnection for a VLSI device.
  6. Kano Isao (Tokyo JPX), Process for forming a multilayer wiring conductor structure in semiconductor device.
  7. Cote William J. (Poughquag NY) Lee Pei-Ing P. (Williston VT) Sandwick Thomas E. (Hopewell Junction NY) Vollmer Bernd M. (Wappingers Falls NY) Vynorius Victor (Pleasant Valley NY) Wolff Stuart H. (Tul, Refractory metal capped low resistivity metal conductor lines and vias.
  8. Brighton Jeffrey E. (Katy TX) Verret Douglas P. (Sugarland TX), Self-aligned tungsten-filled via process and via formed thereby.
  9. Lee Chong E. (Milpitas CA), Self-aligned via and contact interconnect manufacturing method.

이 특허를 인용한 특허 (72)

  1. Progler, Christopher J., Alternating aperture phase shift photomask having light absorption layer.
  2. Progler,Christopher J., Alternating aperture phase shift photomask having light absorption layer.
  3. Singh Bhanwar ; Templeton Michael K. ; Rangarajan Bharath ; Lyons Christopher F. ; Yedur Sanjay K. ; Subramanian Ramkumar, CVD plasma process to fill contact hole in damascene process.
  4. Singh, Bhanwar; Templeton, Michael K.; Rangarajan, Bharath; Lyons, Christopher F.; Yedur, Sanjay K.; Subramanian, Ramkumar, CVD plasma process to fill contact hole in damascene process.
  5. Chan, David Y., Disposable hard mask for phase shift photomask plasma etching.
  6. Chan, David Y., Disposable hard mask for photomask plasma etching.
  7. Chan, David Y., Disposable hard mask for photomask plasma etching.
  8. David Y. Chan, Disposable hard mask for photomask plasma etching.
  9. Lee, Ki Don; Park, Young Joon; Ogawa, Ennis Takashi, Electrically inactive via for electromigration reliability improvement.
  10. Harvey Ian, Integrated circuit device interconnection techniques.
  11. Aaron Schoenfeld ; Rajesh Somasekharan, Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same.
  12. Schoenfeld, Aaron; Somasekharan, Rajesh, Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same.
  13. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit which uses a damascene process for producing staggered interconnect lines.
  14. Horak, David V.; Koburger, Charles W.; Ponoth, Shom; Yang, Chih-Chao, Interconnect structures and methods for back end of the line integration.
  15. Horak, David V.; Koburger, III, Charles W.; Ponoth, Shom; Yang, Chih-Chao, Interconnect structures and methods for back end of the line integration.
  16. Ning, X. J., Method and manufacturing MRAM offset cells in a damascene structure.
  17. Farnworth,Warren M.; Wood,Alan G., Method for fabricating semiconductor components using conductive layer and grooves.
  18. Hussein Makarem A. ; Sivakumar Sam, Method for patterning dual damascene interconnects using a sacrificial light absorbing material.
  19. Makarem A. Hussein ; Sam Sivakumar, Method for patterning dual damascene interconnects using a sacrificial light absorbing material.
  20. Lee Fu-Sheng,TWX ; Chen Chien-Chen,TWX ; Lin Chen-Ting,TWX ; Lu Cheh-Chieh,TWX, Method for processing and integrating copper interconnects.
  21. Ma, Kin F.; Stubbs, Eric T., Method for reducing capacitive coupling between conductive lines.
  22. Rostoker Michael D. ; Muthukumaraswamy Kumaraguru, Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same.
  23. Hsu Chen-Chung,TWX, Method of fabricating a dual damascene structure.
  24. Gau Jing-Horng,TWX, Method of fabricating bit lines by damascene.
  25. Tu An-Chun,TWX ; Tai Shih-Kuan,TWX ; Yeu Tzu-Shih,TWX, Method of low-K/copper dual damascene.
  26. Stamper, Anthony K.; Twombly, John G., Method of manufacturing a micro-electro-mechanical system (MEMS).
  27. Naik Mehul ; Broydo Samuel, Method of producing an interconnect structure for an integrated circuit.
  28. Naik, Mehul; Broydo, Samuel, Method of producing an interconnect structure for an integrated circuit.
  29. Herrin, Russell T.; Maling, Jeffrey C.; Stamper, Anthony K., Methods of manufacture for micro-electro-mechanical system (MEMS).
  30. Havemann Robert H. ; Dixit Girish A., Multilayer metal structure for improved interconnect reliability.
  31. Martin,Patrick M.; Lassiter,Matthew; Taylor,Darren; Cangemi,Michael; Poortinga,Eric, Photomask having an internal substantially transparent etch stop layer.
  32. Kim Hyun Tae SG; Kim Hock Ang SG; Kiok Boone Elgin Quek SG, Pillar process for copper interconnect scheme.
  33. Dang, Dinh; Doan, Thai; Dunbar, III, George A.; He, Zhong-Xiang; Herrin, Russell T.; Jahnes, Christopher V.; Maling, Jeffrey C.; Murphy, William J.; Stamper, Anthony K.; Twombly, John G.; White, Eric J., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  34. Dang, Dinh; Doan, Thai; Maling, Jeffrey C.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  35. Dunbar, III, George A.; He, Zhong-Xiang; Maling, Jeffrey C.; Murphy, William J.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  36. Dunbar, III, George A.; Maling, Jeffrey C.; Murphy, William J.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  37. Dunbar, III, George A.; Maling, Jeffrey C.; Murphy, William J.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  38. Herrin, Russell T.; Jahnes, Christopher V.; Stamper, Anthony K.; White, Eric J., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  39. Herrin, Russell T.; Jahnes, Christopher V.; Stamper, Anthony K.; White, Eric J., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  40. Herrin, Russell T.; Maling, Jeffrey C.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  41. Herrin, Russell T.; Maling, Jeffrey C.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  42. Herrin, Russell T.; Maling, Jeffrey C.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  43. Herrin, Russell T.; Maling, Jeffrey C.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  44. Herrin, Russell T.; Maling, Jeffrey C.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  45. Herrin, Russell T.; Maling, Jeffrey C.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  46. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  47. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  48. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  49. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  50. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  51. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  52. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  53. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  54. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  55. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  56. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  57. Jahnes, Christopher V.; Stamper, Anthony K., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  58. Stamper, Anthony K.; Twombly, John G., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  59. Stamper, Anthony K.; Twombly, John G., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  60. Stamper, Anthony K.; Twombly, John G., Planar cavity MEMS and related structures, methods of manufacture and design structures.
  61. Chao-Cheng Chen TW; Jen-Cheng Liu TW; Jyu-Horng Shieh TW; Chia-Shiung Tsai TW; Bor-Shyang Lin TW, Process for improving copper fill integrity.
  62. Bothra Subhas ; Haskell Jacob, Process for making self-aligned conductive via structures.
  63. Gruening Ulrike ; Radens Carl J. ; Tobben Dirk,DEX, Process for manufacture of trench DRAM capacitor buried plates.
  64. Subhash Gupta SG; Mei-Sheng Zhou SG; Simon Chooi SG; Sangki Hong SG, Reversed damascene process for multiple level metal interconnects.
  65. Farnworth, Warren M.; Wood, Alan G., Semiconductor component and a method of fabricating the semiconductor component.
  66. Kajita Akihiro,JPX ; Matsunaga Noriaki,JPX ; Higashi Kazuyuki,JPX, Semiconductor device and method for manufacturing the same.
  67. Uzoh, Cyprian; Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem, Single exposure in multi-damascene process.
  68. Yang, Chih-Chao; Chen, Hsueh-Chung, Structure and metallization process for advanced technology nodes.
  69. Ponoth, Shom; Horak, David V; Huang, Elbert E; Kanakasabapathy, Sivananda K; Koburger, III, Charles W; Yang, Chih-Chao, Structure for nano-scale metallization and method for fabricating same.
  70. Avanzino Steven ; Gupta Subhash ; Klein Rich ; Luning Scott D. ; Lin Ming-Rin, Subtractive dual damascene semiconductor device.
  71. Farnworth,Warren M.; Wood,Alan G., Test carrier for semiconductor components having conductors defined by grooves.
  72. Jang Syun-Ming,TWX, Top metal and passivation procedures for copper damascene structures.
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