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특허 상세정보

Hardware arrangement of effectively expanding data processing time in pipelining in a microcomputer system and a method

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-013/00   
미국특허분류(USC) 395/800 ; 395/375 ; 395/733 ; 395/775
출원번호 US-0719241 (1996-09-24)
우선권정보 JP-0163706 (1993-07-02)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 50  인용 특허 : 4
초록

A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangment is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the temporary storages which exhibit large delay are replaced by dynamic latches each having a smaller delay time without adversely affecting the operation of the pipelined arrangement.

대표
청구항

A pipelined data processing arrangement having a plurality of stages which are coupled in series, comprising: a first stage for successively issuing a plurality of instructions in synchronism with time slots, said first stage including storage means which, in response to occurrence of an interrupt request, retains therein an instruction applied thereto over one or more time slots which follow a time slot wherein said interrupt request has been issued; a second stage coupled to decode each of said instructions applied thereto from said first stage, said s...

이 특허를 인용한 특허 피인용횟수: 50

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