초록 ▼

A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangment is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the t

A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangment is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the temporary storages which exhibit large delay are replaced by dynamic latches each having a smaller delay time without adversely affecting the operation of the pipelined arrangement.

대표청구항 ▼

A pipelined data processing arrangement having a plurality of stages which are coupled in series, comprising: a first stage for successively issuing a plurality of instructions in synchronism with time slots, said first stage including storage means which, in response to occurrence of an interrupt r

A pipelined data processing arrangement having a plurality of stages which are coupled in series, comprising: a first stage for successively issuing a plurality of instructions in synchronism with time slots, said first stage including storage means which, in response to occurrence of an interrupt request, retains therein an instruction applied thereto over one or more time slots which follow a time slot wherein said interrupt request has been issued; a second stage coupled to decode each of said instructions applied thereto from said first stage, said second stage issuing said interrupt request if pipelined operation should be interrupted, said second stage including dynamic latch means for holding a decoded instruction only during a time slot wherein said decoded instruction has been issued; and a third stage coupled to said second stage, said third stage including: first storage means which, in response to said interrupt request, retains therein a data processing instruction and data, both of which are applied thereto from said second stage, over one time slot which follows a time slot wherein said interrupt request has been issued; and second storage means which, in response to said interrupt request, retains therein a data processing instruction and data, both of which respectively follow said data processing instruction and said data both retained in said first storage means, over one time slot which follows two consecutive time slots at a first time slot of which said interrupt request has been issued.