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Method of fabricating a semiconductor device with a capacitor structure having increased capacitance 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/70
  • H01L-027/00
출원번호 US-0363883 (1994-12-27)
우선권정보 JP-0338592 (1993-12-28)
발명자 / 주소
  • Ueno Kazuyoshi (Tokyo JPX)
출원인 / 주소
  • NEC Corporation (Tokyo JPX 03)
인용정보 피인용 횟수 : 54  인용 특허 : 0

초록

A semiconductor integrated circuit device with a capacitor structure having a large capacitance per unit surface is disclosed, wherein a contact hole is formed in an insulator layer, a metal electrode with or without a rugged surface is formed in the contact hole by an ion beam vapor deposition of m

대표청구항

A method for fabricating a semiconductor integrated circuit device including a switching transistor having a conducting region, comprising the steps of: forming a contact hole in an insulator layer; depositing an electrode metal having a thickness smaller than the diameter of the contact hole on a s

이 특허를 인용한 특허 (54)

  1. Gurtej Sandhu ; Garo J. Derderian, ALD method to improve surface coverage.
  2. Sandhu, Gurtej; Derderian, Garo J., ALD method to improve surface coverage.
  3. Lane,Richard H., Capacitor with noble metal pattern.
  4. Kirlin Peter S. ; Van Buskirk Peter C., Chemical mechanical polishing of FeRAM capacitors.
  5. Josef Willer DE, Circuit arrangement with at least one capacitor.
  6. Jigish D. Trivedi ; Ravi Iyer, Conductive structure in an integrated circuit.
  7. Trivedi, Jigish D.; Iyer, Ravi, Conductive structure in an integrated circuit.
  8. Hidekazu Oda JP; Tomohiro Yamashita JP; Shuichi Ueno JP, Field effect transistor and method of manufacturing same.
  9. Oda Hidekazu,JPX ; Yamashita Tomohiro,JPX ; Ueno Shuichi,JPX, Field effect transistor and method of manufacturing same.
  10. Dennison, Charles H., Field effect transistors and integrated circuitry.
  11. Sandhu, Gurtej; Derderian, Garo J., Film composition.
  12. Harshfield Steven T., Hemispherical grained silicon on conductive nitride.
  13. Steven T. Harshfield, Hemispherical grained silicon on conductive nitride.
  14. Zahurak John K. ; Lane Richard H., Increased interior volume for integrated memory cell.
  15. Sandhu Gurtej S. ; Rolfson J. Brett, Integrated capacitor bottom electrode for use with conformal dielectric.
  16. Sandhu, Gurtej S.; Rolfson, J. Brett, Integrated capacitor bottom electrode for use with conformal dielectric.
  17. Sandhu, Gurtej S.; Rolfson, J. Brett, Integrated capacitor bottom electrode for use with conformal dielectric.
  18. Prall, Kirk; Rhodes, Howard E.; Sharan, Sujit; Sandhu, Gurtel; Ireland, Philip J., Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture.
  19. Prall, Kirk; Rhodes, Howard E.; Sharan, Sujit; Sandhu, Gurtel; Ireland, Philip J., Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture.
  20. Kim,Min Seok, MIM capacitor of semiconductor device and manufacturing method thereof.
  21. Huang Kuo-Tai,TWX ; Hsieh Wen-Yi,TWX ; Yew Tri-Rung,TWX, Method for fabricating a capacitor in a semiconductor device.
  22. Hsu, Sheng Teng; Evans, David Russell, Method for forming a damascene FeRAM cell structure.
  23. Peter Zurcher ; Robert E. Jones, Jr. ; Papu D. Maniar ; Peir Chu, Method for forming a semiconductor device.
  24. Asahina, Michio; Suzuki, Eiji; Matsumoto, Kazuki; Moriya, Naohiro, Method for manufacturing semiconductor devices.
  25. Kinugasa, Akinori, Method of fabricating a semiconductor device and the semiconductor device with a capacitor structure having increased capacitance.
  26. Salman Akram ; Y. Jeff Hu, Method of fabricating silicide pattern structures.
  27. Trivedi Jigish D. ; Iyer Ravi, Method of forming a local interconnect including selectively etched conductive layers and recess formation.
  28. Michaelis Alexander, Method of forming a trench capacitor using a rutile dielectric material.
  29. Lane, Richard H., Method of forming noble metal pattern.
  30. Richard H. Lane, Method of forming noble metal pattern.
  31. Agarwal, Vishnu K.; Derderian, Garo; Sandhu, Gurtej S.; Li, Weimin M.; Visokay, Mark; Basceri, Cem; Yang, Sam, Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers.
  32. Agarwal, Vishnu K.; Derderian, Garo; Sandhu, Gurtej S.; Li, Weimin M.; Visokay, Mark; Basceri, Cem; Yang, Sam, Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers.
  33. Agarwal, Vishnu K.; Derderian, Garo; Sandhu, Gurtej S.; Li, Weimin M.; Visokay, Mark; Basceri, Cem; Yang, Sam, Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers.
  34. Agarwal,Vishnu K.; Derderian,Garo; Sandhu,Gurtej S.; Li,Weimin M.; Visokay,Mark; Basceri,Cem; Yang,Sam, Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers.
  35. Akram, Salman; Hu, Y. Jeff, Methods of fabricating silicide pattern structures.
  36. Yun, Ju-young; Choi, Gil-heyun; Kim, Byung-hee; Lee, Jong-myeong; Yang, Seung-gil; Seo, Jung-hun, Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer.
  37. Yun,Ju young; Choi,Gil heyun; Kim,Byung hee; Lee,Jong myeong; Yang,Seung gil; Seo,Jung hun, Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer.
  38. Li Weimin ; Sandhu Gurtej S., Multiple step methods for forming conformal layers.
  39. Weimin Li ; Gurtej S. Sandhu, Multiple step methods for forming conformal layers.
  40. Hsieh, Chun-I; Damjanovic, Daniel, Process for forming a capacitor structure with rutile titanium oxide dielectric film.
  41. Fazan Pierre C. ; Schuele Paul, Scalable high dielectric constant capacitor.
  42. Fazan Pierre C. ; Schuele Paul, Scalable high dielectric constant capacitor.
  43. Michio Asahina JP; Eiji Suzuki JP; Kazuki Matsumoto JP; Naohiro Moriya JP, Semiconductor device and method for manufacturing semiconductor device.
  44. Asahina Michio,JPX ; Takeuchi Junichi,JPX ; Moriya Naohiro,JPX ; Matsumoto Kazuki,JPX, Semiconductor device and method of fabricating the same.
  45. Chittipeddi Sailesh ; Pearce Charles Walter, Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers.
  46. Sailesh Chittipeddi ; Charles Walter Pearce, Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers.
  47. Sandhu, Gurtej; Derderian, Garo J., Semiconductor device with novel film composition.
  48. Sandhu, Gurtej; Derderian, Garo J., Semiconductor device with novel film composition.
  49. Akram Salman ; Hu Y. Jeff, Silicide pattern structures and methods of fabricating the same.
  50. Akram, Salman; Hu, Y. Jeff, Silicide pattern structures and methods of fabricating the same.
  51. Akram, Salman; Hu, Y. Jeff, Silicide pattern structures and methods of fabricating the same.
  52. Duenas Salvador ; Kola Ratnaji Rao ; Kumagai Henry Y. ; Lau Maureen Yee ; Sullivan Paul A. ; Tai King Lien, Thin film capacitors and process for making them.
  53. Kola Ratnaji Rao ; Tai King Lien, Thin film tantalum oxide capacitors and resulting product.
  54. Isik C. Kizilyalli ; Sailesh M. Merchant ; Joseph R. Radosevich, Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability.
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