초록 ▼

A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a D

A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as SixGe1-x, SixSn1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

대표청구항 ▼

An Insulated-Gate transistor at least having a first conductivity type channel region formed of a first semiconductor, said first conductivity type channel region formed on a first insulating film, a second insulating film formed on the first conductivity type channel region, and a gate electrode fo

An Insulated-Gate transistor at least having a first conductivity type channel region formed of a first semiconductor, said first conductivity type channel region formed on a first insulating film, a second insulating film formed on the first conductivity type channel region, and a gate electrode formed on the second insulating film to control electric current flowing through said first conductivity type channel region, wherein the improvement comprises: a second conductivity type first source region formed of a second semiconductor having a narrower forbidden band gap than that of said first semiconductor; and a second conductivity type second source region formed adjacently on said second conductivity type first source region and formed of said first semiconductor, wherein a top surface of said second conductivity type first source region is formed at a location having a larger depth than that of a depletion layer depth at a minimum depth portion, the depletion layer depth extending from the second insulating film with a maximum gate voltage applied on the gate electrode at an operation condition.