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[미국특허] PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/465
출원번호 US-0606955 (1996-02-26)
발명자 / 주소
  • Yu Chen-Hua (Keelung TWX) Jang Syun-Ming (Hsin-chu TWX)
출원인 / 주소
  • Taiwan Semiconductor Manufactured Company Ltd. (Hsin-chu TWX 03)
인용정보 피인용 횟수 : 57  인용 특허 : 0

초록

This invention provides a method for forming dense electrode patterns having a high aspect ratio in a conductor metal layer. The method uses silicon nitride deposited using plasma enhanced chemical vapor deposition, PECVD, as an etch stop mask to protect the conductor metal and anti reflection coati

대표청구항

A method of forming electrode patterns, comprising the steps of: providing an integrated circuit element having devices formed therein; providing a base dielectric layer formed on said integrated circuit element; forming a conductor metal layer on said base dielectric layer; forming an antireflectio

이 특허를 인용한 특허 (57)

  1. Hsu Chen-Chung,TWX, Dual damascene manufacturing process.
  2. Salmon, Peter C., Electronic assembly with electronic compontent and interconnection assembly connected via conductive bump and mating well.
  3. Salmon, Peter C., Electronic system modules and method of fabrication.
  4. Salmon, Peter C., Electronic system modules and method of fabrication.
  5. Salmon, Peter C., Electronic system modules and method of fabrication.
  6. Salmon, Peter C., Electronic system modules and method of fabrication.
  7. Salmon, Peter C., Fabrication method for electronic system modules.
  8. Salmon,Peter C., Fabrication method for electronic system modules.
  9. Hu Chu-Wei,TWX ; Lin Chung-Te,TWX ; Hou Chin-Shan,TWX ; Pan Kuo-Hua,TWX, Formation of a thin oxide protection layer at poly sidewall and area surface.
  10. Jang Syun-Ming,TWX ; Huang Ming-Hsin,TWX, Hard masking method for forming patterned oxygen containing plasma etchable layer.
  11. Jang,Syun Ming; Huang,Ming Hsin, Hard masking method for forming patterned oxygen containing plasma etchable layer.
  12. Liu, Chih Chien; Tseng, Ta Shan; Shieh, W. B.; Wu, J. Y.; Lur, Water; Sun, Shih Wei, High density plasma chemical vapor deposition process.
  13. Liu, Chih-Chien; Tseng, Ta-Shan; Shieh, Wen Bin; Wu, Juan-Yuan; Lur, Water; Sun, Shih-Wei, High density plasma chemical vapor deposition process.
  14. Liu, Chih-Chien; Tseng, Ta-Shan; Shieh, Wen-Bin; Wu, Juan-Yuan; Lur, Water; Sun, Shih-Wei, High density plasma chemical vapor deposition process.
  15. Liu,Chih Chien; Tseng,Ta Shan; Shieh,Wen Bin; Wu,Juan Yuan; Lur,Water; Sun,Shih Wei, High density plasma chemical vapor deposition process.
  16. Liu,Chih Chien; Tseng,Ta Shan; Shieh,Wen Bin; Wu,Juan Yuan; Lur,Water; Sun,Shih Wei, High density plasma chemical vapor deposition process.
  17. Herner, S. Brad; Mahajani, Maitreyee, High-density nonvolatile memory.
  18. Herner, S. Brad; Mahajani, Maitreyee, High-density nonvolatile memory.
  19. Herner, Scott Brad; Mahajani, Maitreyee, High-density nonvolatile memory and methods of making the same.
  20. Herner, Scott Brad; Radigan, Steven J., Method for forming a nonvolatile memory cell comprising a reduced height vertical diode.
  21. Mizushima Kazuyuki,JPX, Method for manufacturing a through hole.
  22. Chris Ting TW; Janet Yu TW, Method for metal etch using a dielectric hard mask.
  23. Eckert, Stefan; Goller, Klaus; Wendt, Hermann, Method for producing a layer arrangement.
  24. Thomas Rohr DE; Christine Dehm DE; Carlos Mazure-Espejo FR, Method of fabricating semiconductor components.
  25. Liu, Chung-Shi; Shue, Shau-Lin; Yu, Chen-Hua, Method to improve reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and aluminum-copper-TiN layers in integrated circuits.
  26. Dunton,Samuel V.; Herner,S. Brad, Method to minimize formation of recess at surface planarized by chemical mechanical planarization.
  27. Wang Fei ; Lyons Christopher F. ; Nguyen Khanh B. ; Bell Scott A. ; Levinson Harry J. ; Yang Chih Yuh, Method using a thin resist mask for dual damascene stop layer etch.
  28. En William G. ; Ngo Minh Van ; Karlsson Olov B., Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process.
  29. Violette Michael P. ; Tang Sanh ; Smith Daniel M., Methods for use in formation of titanium nitride interconnects.
  30. Violette Michael P. ; Tang Sanh ; Smith Daniel M., Methods for use in formation of titanium nitride interconnects and interconnects formed using same.
  31. Herner, Scott Brad; Mahajani, Maitreyee, Methods of making a high-density nonvolatile memory.
  32. Plat Marina V. ; Hao Ming-Yin, Minimization of line width variation in photolithography.
  33. Cheng Jerry ; Wang Fei, Nitride etch using N.sub.2 /Ar/CHF.sub.3 chemistry.
  34. Herner, S. Brad; Radigan, Steven J., Nonvolatile memory cell comprising a reduced height vertical diode.
  35. Herner, S. Brad; Radigan, Steven J., Nonvolatile memory cell comprising a reduced height vertical diode.
  36. Herner, S. Brad; Bandyopadhyay, Abhijit, Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material.
  37. Herner, S. Brad; Bandyopadhyay, Abhijit, Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material.
  38. Herner, Scott Brad; Bandyopadhyay, Abhijit, Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material.
  39. Herner, S. Brad; Walker, Andrew J., Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states.
  40. Herner, Scott Brad; Walker, Andrew, Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states.
  41. Shields Jeffrey A. ; Anderson Mark, Pad etch process capable of thick titanium nitride arc removal.
  42. Höhnsdorf, Falko, Process for producing contact holes on a metallization structure.
  43. Huang, Jui-Tsen, Removing silicon oxynitride of polysilicon gates in fabricating integrated circuits.
  44. Radens Carl J. ; Fairchok Cynthia A., Selective oxide-to-nitride etch process using C.sub.4 F.sub.8 /CO/Ar.
  45. Liu Meng-Chang,TWX, Self-aligned connection to underlayer metal lines through unlanded via holes.
  46. Fukada Tetsuo,JPX ; Mori Takeshi,JPX ; Hasegawa Makiko,JPX ; Toyoda Yoshihiko,JPX, Semiconductor device having interconnection and adhesion layers.
  47. Ikeda, Masanobu, Semiconductor device manufacturing method of forming an etching stopper film on a diffusion prevention film at a higher temperature.
  48. Doshi Vikram N. ; Niuya Takayuki ; Yang Ming, Silicon nitride dopant diffusion barrier in integrated circuits.
  49. Scheuerlein, Roy E., Structure and method for biasing phase change memory array for reliable writing.
  50. Scheuerlein, Roy E., Structure and method for biasing phase change memory array for reliable writing.
  51. Chary, Sathya; Lucow, Ewelina; Siala, Sabeur; Suarez, Ferran; Torabi, Ali; Zhang, Lan, Surface mount solar cell with integrated coverglass.
  52. Cheng Jerry ; Wang Fei, Tantalum barrier metal removal by using CF.sub.4 /o.sub.2 plasma dry etch.
  53. Kirchhoff Markus M.,DEX ; Hanebeck Jochen,DEX, Techniques for etching a silicon dioxide-containing layer.
  54. Violette Michael P. ; Tang Sanh ; Smith Daniel M., Titanium nitride interconnects.
  55. Yeh,Fang Yu; Lin,Chi; Chen,Chia Yao, Two-step GC etch for GC profile and process window improvement.
  56. Hsu Shih-Ying,TWX, Unlanded via process.
  57. Lucow, Ewelina; Zhang, Lan; Chary, Sathya; Suarez, Ferran, Via etch method for back contact multijunction solar cells.

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