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특허 상세정보

Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instruc

국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판) G06F-009/45   
미국특허분류(USC) 284/383 ; 395/705
출원번호 US-0443653 (1995-05-18)
발명자 / 주소
출원인 / 주소
인용정보 피인용 횟수 : 175  인용 특허 : 5
초록

A compiler that facilitates efficient insertion of explicit data prefetch instructions into loop structures within applications uses simple address expression analysis to determine data prefetching requirements. Analysis and explicit data cache prefetch instruction insertion are performed by the compiler in a machine-instruction level optimizer to provide access to more accurate expected loop iteration latency information. Such prefetch instruction insertion strategy tolerates worst-case alignment of user data structures relative to data cache lines. Exe...

대표
청구항

A method for mitigating or eliminating cache misses in a low level optimizer, comprising the steps of: performing loop body analysis; unrolling loops to reduce prefetch instruction overhead; identifying uniformly generated equivalence classes of memory references in a code stream, where said equivalence classes represent disjoint sets of memory references occurring in a loop whose address expressions can be expressed as a linear function of the same basic loop induction variable and are known to differ only by a compile time constant, allowing the detect...

이 특허를 인용한 특허 피인용횟수: 175

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