[특허]Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors

Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03K-019/177
출원번호	US-0730351 (1996-10-15)
발명자 / 주소	McClintock Cameron Cliff Richard G. Leong William
출원인 / 주소	Altera Corporation
대리인 / 주소	Fish & NeaveJackson
인용정보	피인용 횟수 : 31 인용 특허 : 0

초록 ▼

A programmable logic array integrated circuit device has regions of programmable logic grouped in blocks disposed on the device in a two-dimensional array of intersecting rows and columns. Each block includes a relatively small number of logic regions to reduce the size and complexity of the local feedback circuity required in the block. Interconnection conductors extend along each row and column of blocks. Some of these conductors are segmented along their length to permit independent use of each segment. When longer interconnections are required, however, adjacent segments can be interconnected by programmable bi-directional switches between the segments.

대표청구항 ▼

[ The invention claimed is:] [1.] A programmable logic array integrated circuit device comprising:a plurality of logic regions, each of which has a plurality of input terminals and at least one output terminal, and each of which is programmable to produce at its output terminal an output logic signal which is any of a plurality of logic functions of input logic signals applied to its input terminals, said logic regions being grouped in a plurality of blocks of said logic regions such that each of said blocks includes a respective subplurality of adjacent ones of said logic regions, said blocks being disposed on said integrated circuit in a two-dimensional array of intersecting rows and columns of said blocks, each of said rows being subdivided into a plurality of sub-rows of said blocks such that each of said sub-rows includes a respective subplurality of adjacent ones of said blocks in the row of which that sub-row is a part;a plurality of sub-row conductors associated with each of said sub-rows, each of said sub-row conductors extending along the length of the associated sub-row;a plurality of column conductors associated with each of said columns, each of said column conductors extending along the length of the associated column;a plurality of block feeding conductors associated with each of said blocks, each of said block feeding conductors extending along the logic regions of the associated block;a first programmable switch array associated with each of said pluralities of block feeding conductors for selectively connecting said block feeding conductors to sub-row conductors associated with the sub-row which includes the block associated with said block feeding conductors;a second programmable switch array associated with each of said logic regions for selectively connecting the input terminals of said logic region to block feeding conductors associated with the block which includes said logic region;a third programmable switch array associated with each of said logic regions for selectively applying the logic output signal of said logic region to sub-row and column conductors respectively associated with the sub-row and column which include the block that includes said logic region; anda fourth programmable switch array associated with each adjacent pair of sub-rows in each row for selectively connecting sub-row conductors associated with one of the associated pair of sub-rows to sub-row conductors associated with the other of the associated pair of sub-rows.

이 특허를 인용한 특허 (31)

Lewis, David, High speed testing of integrated circuits including resistive elements.
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Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; Jefferson David Edward, Input/output circuitry for programmable logic devices.
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Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; Jefferson David Edward, Input/output circuitry for programmable logic devices.
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Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection and input/output resources for programable logic integrated circuit devices.
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Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.
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Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.
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Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.
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Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.
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Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Maruri,Victor; Patel,Rakesh, Interconnection and input/output resources for programmable logic integrated circuit devices.
상세보기
Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.
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Bertolet Allan Robert ; Clinton Kim P.N. ; Gould Scott Whitney ; Keyser III Frank Ray ; Reny Timothy Shawn ; Zittritsch Terrance John, Method and system for layout and schematic generation for heterogeneous arrays.
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Lee,Andy L.; McClintock,Cameron; Johnson,Brian; Cliff,Richard; Reddy,Srinivas; Lane,Chris; Leventis,Paul; Betz,Vaughn Timothy; Lewis,David, Methods for designing PLD architectures for flexible placement of IP function blocks.
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Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
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Lee, Andy L.; McClintock, Cameron R.; Johnson, Brian D.; Cliff, Richard G.; Reddy, Srinivas T.; Lane, Christopher F.; Leventis, Paul; Betz, Vaughn; Lewis, David, PLD architecture for flexible placement of IP function blocks.
상세보기
Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
상세보기
Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
상세보기
Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Chris; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
상세보기
Lee, Andy L.; McClintock, Cameron; Johnson, Brian; Cliff, Richard; Reddy, Srinivas; Lane, Christopher; Leventis, Paul; Betz, Vaughn Timothy; Lewis, David, PLD architecture for flexible placement of IP function blocks.
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Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit architectures.
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Cliff Richard G. ; Heile Francis B. ; Sung Chiakang ; Wang Bonnie I. ; Pedersen Bruce B., Programmable logic array integrated circuit architectures.
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Richard G. Cliff ; Francis B. Heile ; Joseph Huang ; Christopher F. Lane ; Fung Fung Lee ; Cameron McClintock ; David W. Mendel ; Ninh D. Ngo ; Bruce B. Pedersen ; Srinivas T. Reddy ; Chiak, Programmable logic array integrated circuit architectures.
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Jefferson, David E.; McClintock, Cameron; Schleicher, James; Lee, Andy L.; Mejia, Manuel; Pedersen, Bruce B.; Lane, Christopher F.; Cliff, Richard G.; Reddy, Srinivas T., Programmable logic device architectures with super-regions having logic regions and a memory region.
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David E. Jefferson ; Cameron McClintock ; James Schleicher ; Andy L. Lee ; Manuel Mejia ; Bruce B. Pederson ; Christopher F. Lane ; Richard G. Cliff ; Srinivas T. Reddy, Programmable logic device architectures with super-regions having logic regions and memory region.
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Lewis, David, Routing and programming for resistive switch arrays.
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Lewis, David, Routing and programming for resistive switch arrays.
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Lewis, David, Routing and programming for resistive switch arrays.
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Lewis, David M.; Leventis, Paul; Lee, Andy L.; Johnson, Brian D.; Cliff, Richard; Reddy, Srinivas T.; Lane, Christopher F.; McClintock, Cameron R.; Betz, Vaughn; Wysocki, Chris; Marquardt, Alexander , Routing architecture for a programmable logic device.
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Lewis, David M.; Leventis, Paul; Lee, Andy L.; Johnson, Brian D.; Cliff, Richard; Reddy, Srinivas T.; Lane, Christopher F.; McClintock, Cameron R.; Betz, Vaughn; Wysocki, Chris; Marquardt, Alexander , Routing architecture for a programmable logic device.
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Lewis, David M.; Betz, Vaughn; Leventis, Paul; Chan, Michael; McClintock, Cameron R.; Lee, Andy L.; Lane, Christopher F.; Reddy, Srinivas T.; Cliff, Richard, System and method for optimizing routing lines in a programmable logic device.
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Johnson, Brian D.; Lee, Andy L.; McClintock, Cameron; Powell, Giles V.; Leventis, Paul, Use of dangling partial lines for interfacing in a PLD.
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Johnson, Brian D.; Lee, Andy L.; McClintock, Cameron; Powell, Giles V.; Leventis, Paul, Use of dangling partial lines for interfacing in a PLD.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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연합인증

Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors 원문보기

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Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors 원문보기

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이 특허를 인용한 특허 (31)

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