이 특허를 인용한 특허 (76)

1. Lur,Water; Lee,David; Wang,Kuang Chih; Yang,Ming Sheng, Air gap for tungsten/aluminum plug applications.

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2. Lur,Water; Lee,David; Wang,Kuang Chih; Yang,Ming Sheng, Air gap formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device.

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3. Lur, Water; Lee, David; Wang, Kuang-Chih; Yang, Ming-Sheng, Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device.

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4. Anderson, Brent A.; Bryant, Andres; Gambino, Jeffrey P.; Stamper, Anthony K., Air-gap insulated interconnections.

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5. Anderson,Brent A.; Bryant,Andres; Gambino,Jeffrey P.; Stamper,Anthony K., Air-gap insulated interconnections.

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6. Dubin, Valery M.; Moon, Peter K., Apparatus for an improved air gap interconnect structure.

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7. Derryl D. J. Allman ; Brian Bystedt, Capacitor with multiple-component dielectric and method of fabricating same.

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8. Allman, Derryl D. J.; Mansour, Nabil; Saopraseuth, Ponce, Capacitor with stoichiometrically adjusted dielectric and method of fabricating same.

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9. Anthony K. Stamper, Copper conductive line with redundant liner and method of making.

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10. McTeer Allen, Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with c.

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11. McTeer Allen, Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with copper.

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12. Zhao,Bin; Brongo,Maureen R., Damascene interconnect structure and fabrication method having air gaps between metal lines and metal layers.

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13. Shroff, Mehul; Benard, Gerald G.; Grigg, Philip, Dielectric between metal structures and method therefor.

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14. Edelstein Daniel C. ; Dalton Timothy J. ; Gaudiello John G. ; Krishnan Mahadevaiyer ; Malhotra Sandra G. ; McGlashan-Powell Maurice ; O'Sullivan Eugene J. ; Sambucetti Carlos J., Dual etch stop/diffusion barrier for damascene interconnects.

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15. Yang, Bin; Ng, Man Fai, ETSOI with reduced extension resistance.

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16. Tran Khanh, Electromigration resistant patterned metal layer gap filled with HSQ.

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17. Tran Khanh, Electromigration resistant patterned metal layer gap filled with HSQ.

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18. Gregory A. Johnson ; Kunal Taravade ; Gayle Miller, Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same.

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19. Chiang, Chien; Fraser, David B., In-plane on-chip decoupling capacitors and method for making same.

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20. Chiang, Chien; Fraser, David B., In-plane on-chip decoupling capacitors and method for making same.

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21. Shroff, Mehul; Benard, Gerald G.; Grigg, Philip, Integrated circuit device having sidewall spacers along conductors.

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22. Harvey Ian, Integrated circuit device interconnection techniques.

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23. Li, Weidan; Catabay, Wilbur G.; Hsia, Wei-Jen, Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines.

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24. Ellis Lee TW; Shih-Wei Sun TW, Interconnect structure with air gap compatible with unlanded vias.

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25. Allman, Derryl D. J.; Fuchs, Kenneth, Interconnect-embedded metal-insulator-metal capacitor.

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26. Derryl D. J. Allman ; John Q. Walker ; Verne C. Hornback ; Todd A. Randazzo, Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same.

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27. Hasegawa Toshiaki,JPX, Interlayer insulating film for semiconductor device.

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28. Sandhu Gurtej ; Srinivasan Anand ; Iyer Ravi, Interlevel dielectric structure.

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29. Sandhu, Gurtej; Srinivasan, Anand; Iyer, Ravi, Interlevel dielectric structure.

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30. Sandhu, Gurtej; Srinivasan, Anand; Iyer, Ravi, Interlevel dielectric structure and method of forming same.

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31. Wollesen Donald L., Low capacitance interconnection.

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32. Wollesen Donald L., Low capacitance interconnection.

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33. Jang Syun-Ming,TWX, Low dielectric constant intermetal dielectric (IMD) by formation of air gap between metal lines.

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34. Catabay, Wilbur G.; Hsia, Wei-Jen; Li, Weidan; Zhao, Joe W., Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same.

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35. Buynoski, Matthew S., Low dielectric metal silicide lined interconnection system.

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36. Buynoski Matthew S., Low dielectric semiconductor device with rigid lined interconnection system.

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37. Buynoski Matthew S., Low dielectric semiconductor device with rigid, conductively lined interconnection system.

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38. Catabay, Wilbur G.; Schinella, Richard, Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning.

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39. Dubin,Valery M.; Moon,Peter K., Method and apparatus for an improved air gap interconnect structure.

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40. Robert J. Gauthier, Jr. ; Dominic J. Schepis ; Steven H. Voldman, Method and structure of high and low K buried oxide for SOI technology.

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41. Xing Guoqiang ; Brennan Kenneth D., Method for air gap formation by plasma treatment of aluminum interconnects.

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42. Dubin, Valery M.; Moon, Peter K., Method for an improved air gap interconnect structure.

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43. Ellis Lee TW; Shih-Wei Sun TW, Method for forming an interconnect structure with air gap compatible with unlanded vias.

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44. Rostoker Michael D. ; Muthukumaraswamy Kumaraguru, Method of controlling critical dimension of features in integrated circuits (ICS), ICS formed by the method, and systems utilizing same.

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45. Gayle W. Miller ; Kenneth P. Fuchs, Method of electrically connecting and isolating components with vertical elements extending between interconnect layers in an integrated circuit.

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46. Gardner Mark I. ; Kadosh Daniel, Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines.

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47. Wang Chih-Jung,TWX ; Liu Lu-Min,TWX, Method of fabricating an unlanded via.

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48. Sandhu Gurtej ; Srinivasan Anand ; Iyer Ravi, Method of forming an interlevel dielectric.

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49. Daniel C. Edelstein ; Timothy J. Dalton ; John G. Gaudiello ; Mahadevaiyer Krishnan ; Sandra G. Malhotra ; Maurice McGlashan-Powell ; Eugene J. O'Sullivan ; Carlos J. Sambucetti, Method of forming barrier layers for damascene interconnects.

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50. Buynoski Matthew S., Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system.

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51. Buynoski Matthew S., Method of forming low dielectric tungsten lined interconnection system.

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52. Lin Shih-Chi,TWX ; Chen Yen-Ming,TWX ; Chang Juin-Jie,TWX ; Huang Kuei-Wu,TWX, Method of manufacturing air gap in multilevel interconnection.

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53. Quek, Shyue-Fong; Ang, Ting Cheong; Ong, Duay Ing; Loong, Sang Yee, Method of vacuum packaging a semiconductor device assembly.

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54. Quek Shyue Fong,MYX ; Ang Ting Cheong,SGX ; Chan Lap ; Loong Sang Yee,SGX, Method to form, and structure of, a dual damascene interconnect device.

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55. Li Jianxun,SGX ; Zhou Mei Sheng,SGX ; Xu Yi,SGX ; Chooi Simon,SGX, Method to prevent degradation of low dielectric constant material in copper damascene interconnects.

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56. Chia-Shiung Tsai TW; Yao-Yi Cheng TW; Hun-Jan Tao TW, Methods of adhesion promoter between low-K layer and underlying insulating layer.

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57. Kevin S. Petrarca ; Rebecca D. Mih, Microprocessor having air as a dielectric and encapsulated lines.

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58. Ahn, Kie Y.; Forbes, Leonard, Multilevel interconnect structure with low-k dielectric.

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59. Ahn,Kie Y.; Forbes,Leonard, Multilevel interconnect structure with low-k dielectric.

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60. Hornbeck, Verne C.; Allman, Derryl D. J., On-chip graded index of refraction optical waveguide and damascene method of fabricating the same.

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61. Allman Derryl D. J. ; Hornbeck Verne C., On-chip multiple layer vertically transitioning optical waveguide and damascene method of fabricating the same.

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62. Derryl D. J. Allman ; Verne C. Hornbeck, On-chip multiple layer vertically transitioning optical waveguide and damascene method of fabricating the same.

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63. Hornbeck Verne C. ; Allman Derryl D. J., On-chip single layer horizontal deflecting waveguide and damascene method of fabricating the same.

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64. Verne C. Hornbeck ; Derryl D. J. Allman, On-chip single layer horizontal deflecting waveguide and damascene method of fabricating the same.

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65. Harvey Ian, Oxide etch stop techniques for uniform damascene trench depth.

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66. Zeng, Jun; Darwish, Mohamed N.; Blanchard, Richard A., Power device structures and methods using empty space zones.

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67. Honjo, Mitsuru; Yamazaki, Natsuko, Printed circuit board.

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68. Givens, John H., Reduced RC between adjacent substrate wiring lines.

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69. Givens John H., Reduced RC delay between adjacent substrate wiring lines.

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70. Usami Tatsuya,JPX, Semiconductor device and fabrication process thereof.

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71. Usami Tatsuya,JPX, Semiconductor device and fabrication process thereof.

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72. Tatsuya Usami JP, Semiconductor device having through holes selectively through isolation material covering wirings that are relatively far apart.

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73. Kohyama Yusuke,JPX, Semiconductor device using dual damascene technology and method for manufacturing the same.

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74. Kohyama Yusuke,JPX, Semiconductor device using dual damascene technology and method for manufacturing the same.

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75. Gardner Mark I. ; Gilmer Mark C., Transistor having an etchant-scalable channel length and method of making same.

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76. Hiroshi Yamamoto JP, Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure.

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