초록 ▼

A combination of a doping process and the use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit o

A combination of a doping process and the use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.

대표청구항 ▼

[ What is claimed is:] [1.] A semiconductor device comprising:a substrate having an insulating surface;an active matrix circuit, having at least one first thin film transistor, formed on the insulating surface; anda peripheral circuit, having at least one second thin film transistor, formed on the i

[ What is claimed is:] [1.] A semiconductor device comprising:a substrate having an insulating surface;an active matrix circuit, having at least one first thin film transistor, formed on the insulating surface; anda peripheral circuit, having at least one second thin film transistor, formed on the insulating surface, for driving the active matrix circuit,wherein each of the first and second thin film transistors comprisessource and drain regions,a channel region provided between the source and drain regions,a gate electrode formed over the active region,an insulating film comprising an oxide of the gate electrode formed on at least side surfaces thereof, andside insulators formed adjacent to only sides of the gate electrode with said insulating film interposed therebetween, andwherein the first thin film transistor further comprises offset regions formed below said side insulators without doped impurities between the source region and the channel region and between the channel region and the drain region, said offset region comprising the same material as and having the same conductivity as said channel region, andthe second thin film transistor further comprises lightly doped regions formed between the source region and the channel region and between the channel region and the drain region.