초록 ▼

Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads an

Assemblies and methods for interconnecting integrated circuits, particularly prepackaged ones, are disclosed. A multi-level electrical assembly--composed of a pin carrier, a set of pads, such as for receiving a surface-mounted integrated circuit, and a set of conductive pathways coupling the pads and the pins--can connect one or more integrated circuits to the socket or other attachment area of a circuit board. The pathways pass through a multi-layered interconnect board, which can be configured to permit any translation of pads to pins for different purposes, or to permit the coupling of additional circuit elements, such as a coprocessor or passive circuits, to the pathways. Inventive methods for forming the assemblies, and inventive systems in which the embodiment of the assembly can be used to increase circuit board density, are also disclosed.

대표청구항 ▼

[ I claim:] [1.] A multi-level electrical assembly for coupling at least one integrated circuit having a plurality of electrically conductive leads to at least one attachment area of a circuit board comprising:(a) an interconnect board, including an electrically insulating substrate, having a top su

[ I claim:] [1.] A multi-level electrical assembly for coupling at least one integrated circuit having a plurality of electrically conductive leads to at least one attachment area of a circuit board comprising:(a) an interconnect board, including an electrically insulating substrate, having a top surface, a flat bottom surface, and two cores;(b) an electrically insulating pin carrier disposed generally parallel to the interconnect board;(c) a plurality of electrically conductive pins held by the pin carrier parallel to each other, perpendicular with the pin carrier, and in relative positions predetermined so as to align with receptacles of a circuit board;(d) a plurality of electrically conductive receiving devices configured to receive leads of an integrated circuit supported on one of the surfaces of the interconnect board;(e) a plurality of electrically conductive flat pads on the bottom surface of the interconnect board;(f) wherein the area within a first perimeter line surrounding all of the receiving devices on the surface of the interconnect board that supports the receiving devices is larger than the area within a second perimeter line surrounding all of the flat pads on the bottom surface of the interconnect board;(g) a plurality of contacts electrically coupling ends of selected of the pins to the pads and physically holding the pin ends against the pads, wherein no portion of the pins extends beyond the flat bottom surface of the interconnect board; and(h) a plurality of electrically conductive pathways, at least in part supported by the interconnect board, at least some of which pathways electrically couple at least one of the contacts to at least one of the receiving devices;(i) wherein the electrically conductive pathways form three distinct pattern on (1) two exterior surfaces of the board having conductive material disposed on selected lateral regions of each, and (2) at least one buried surface between the cores having conductive material disposed in selected lateral regions and(j) wherein the electrically conductive pathways include a plurality of conductive vias connecting conductive material of the exterior surfaces with conductive material of the buried surface.