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Method of forming a pinned module 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01R-009/16
  • H05K-003/30
  • H05K-003/36
출원번호 US-0457413 (1995-06-01)
발명자 / 주소
  • Kman Stephen Joseph
  • Stubecki John Arthur
  • Sondej William Richard
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Calfee, Halter & Griswold
인용정보 피인용 횟수 : 23  인용 특허 : 43

초록

An electrical connection pin blank having at least one compliant section is affixed to a first circuit board by compressive deformation in such a way that the compliant section of the pin blank projects outwardly from the surface of the first circuit board. The end of the pin projecting from the fir

대표청구항

[ We claim:] [1.] A process for forming a pinned module assembly comprising:(1) providing a substrate defining a first surface, a second surface spaced from said first surface, and a plurality of holes for receiving a plurality of electrical connector pin blanks having a first end portion and a seco

이 특허에 인용된 특허 (43)

  1. Emerick Alan J. (Warren Center PA) Marsh Eugene L. (Endicott NY) Miller Thomas L. (Vestal NY) Zalesinski Jerzy M. (Endicott NY), Affixing pluggable pins to a ceramic substrate.
  2. Andros Frank E. (Binghamton NY) Kerjilian Ghazaros K. (Vestal NY) Stevens Bert E. (Vestal NY) Tomek Reinhold E. (Endwell NY), Air-cooled hybrid electronic package.
  3. Bindra Perminder S. (South Salem NY) Lueck Peter J. (Leonberg NY DEX) Naegele Eberhard H. (Johnson City NY), Alignment-registration tool for fabricating multi-layer electronic packages.
  4. Darrow, Russell E.; Ingraham, Glenn J.; Larnerd, John D.; Nesky, Robert W., Apparatus for connecting contact pins to a substrate.
  5. Fey Donald (Vestal NY) Legg John T. (Glen Aubrey NY) Pierson Mark V. (Binghamton NY), Automatic extrusion pinning method and apparatus.
  6. Ushifusa Nobuyuki (Hitachi JPX) Shinohara Hiroichi (Hitachi JPX) Nagayama Kousei (Ibaraki JPX) Ogihara Satoru (Hitachi JPX) Soga Tasao (Hitachi JPX), Ceramic multilayer circuit board and semiconductor module.
  7. Gow ; 3rd John (Owego NY) Hoffman Herman S. (Apalachin NY) Stephans Earl (Chenango Forks NY), Cermet resistor trimming method.
  8. Lovendusky ; Charles Michael, Circuit board contact.
  9. Sitzler Fred C. (Hanover PA), Circuit board contact element and compliant section thereof.
  10. Kendall Jerry A. (Lewisville TX) Webb David M. (Lewisville TX), Compliant electrical connector pin.
  11. Charsky Ronald S. (Binghamton NY) Olson Leonard T. (Centreville VA) Pagnani David P. (Apalachin NY), Composite dielectric structure for optimizing electrical performance in high performance chip support packages.
  12. Neidich Douglas A. (Harrisburg PA), Compressible core electrical connector.
  13. Long William B. (Camp Hill PA) Shannon Suel G. (Harrisburg PA), Electrical connector for interconnecting printed circuit boards.
  14. Legrady Janos (Putnam Valley NY), Electrical terminal with frangible mounting leg and method of forming the same.
  15. Joseph Charles A. (Candor NY) Petrozello James R. (Endicott NY), Electrically conductive composition and use thereof.
  16. Feilchenfeld Natalie B. (Endicott NY) Fuerniss Stephen J. (Endicott NY) Glenning John J. (Vestal NY) Pawlowski Walter P. (Endicott NY) Phelan Giana M. (Endicott NY) Rickerl Paul G. (Endicott NY), Forming a polymide pattern on a substrate.
  17. Arisaka Hiroshi (Tokyo JPX), High frequency electrical connector comprising multilayer circuit board.
  18. Ozawa Takashi (Tokyo JPX) Munakata Ichiro (Kawasaki JPX) Takagi Hiroaki (Kawasaki JPX) Kozaki Ryoichi (Kawasaki JPX), Hybrid IC device.
  19. Whitehead Graham K. (Ipswich GB2) Taylor Kenneth (East Barnet GB2), Integrated circuit chip carrier.
  20. Gedney ; Ronald W. ; Rasile ; John, Integrated circuit package.
  21. Frankeny Jerome A. (Taylor TX) Frankeny Richard F. (Austin TX) Hermann Karl (Austin TX) Imken Ronald L. (Round Rock TX), Integrated circuit packaging using flexible substrate.
  22. Kraus Charles J. (Poughkeepsie NY) Wu Leon L. (Hopewell Junction NY), Interposer chip technique for making engineering changes between interconnected semiconductor chips.
  23. Gedney ; Ronald Walker ; Rodite ; Robert Richard, Metallized ceramic and printed circuit module.
  24. Desai Kishor V. (Vestal NY) Franchak Nelson P. (Binghamton NY) Katyl Robert H. (Vestal NY) Kohn Harold (Endwell NY) Sholtes Tamar A. (Endicott NY) Veeraraghavan Vilakkudi G. (Endicott NY) Woychik Cha, Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate.
  25. Koopman Nicholas George (Hopewell Junction NY), Method for making conduction-cooled circuit package.
  26. Mukherjee Shyama P. (Vestal NY), Method for producing a ceramic.
  27. Dougherty William E. (Wappingers Falls NY) Greer Stuart E. (Poughkeepsie NY), Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations di.
  28. Aakalu Nandakumar G. (Poughkeepsie NY) Rittmiller Lawrence A. (Saugerties NY), Non-bleeding thixotropic thermally conductive material.
  29. Chiang Jung-Shan (Taipei TWX), Pin grid array adaptor mounting hardware.
  30. Pierson Mark V. (Binghamton NY), Pin retention method and apparatus.
  31. Macek Joseph S. (Binghamton NY) Petrozello James R. (Endicott NY) Tomek Reinhold E. (Endwell NY), Pin with tubular elliptical compliant portion and method for affixing to mating receptacle.
  32. Lin Paul T. (Austin TX), Process for making a hermetic low cost pin grid array package.
  33. Donson William A. (Endicott NY) Ellerson James V. (Endicott NY) Hammer Richard B. (Apalachin NY) Lafer William (Chenango Bridge NY) Snyder Keith A. (Vestal NY), Providing circuit lines on a substrate.
  34. Darrow Russell E. (Newark Valley NY) Memis Irving (Vestal NY) Poliak Richard M. (Endwell NY), Sealing of integrated circuit modules.
  35. Sugimoto Masahiro (Yokosuka JPX) Wakabayashi Tetsushi (Yokohama JPX) Muratake Kiyoshi (Kawasaki JPX), Semiconductor device.
  36. Soga Tasao (Hitachi JPX) Goda Marahiro (Hitachi JPX) Nakano Fumio (Hitachi JPX) Kushima Tadao (Ibaraki JPX) Ushifusa Nobuyuki (Hitachi JPX) Kobayashi Fumiyuki (Sagamihara JPX) Sawahata Mamoru (Hitach, Semiconductor resin package structure.
  37. Darrow Russell E. (Endicott NY) Emerick Alan J. (Warren Center PA) Larnerd John D. (Owego NY), Solder leveling technique.
  38. Ameen ; Joseph G. ; Elmore ; Glenn V. ; Peter ; Anthony E., Strippable solder mask material comprising polysulfone, silicon dioxide filler, and solvent.
  39. Adwalpalker Avinash S. (Stormville NY) Harvilchuck Joseph M. (Billings NY) Ranalli Joseph R. (Fishkill NY) Rich David W. (Middletown NY), Stripped gold plating process.
  40. Simpson John P. (Apalachin NY), Surface mounted array strain relief device.
  41. Horvath Joseph L. (Poughkeepsie NY), Thermal conduction element for semiconductor devices.
  42. Nakanishi Keiichirou (Kokubunji JPX) Yamamoto Masakazu (Hadano JPX) Yamada Minoru (Hanno JPX), Thick film and thin film composite substrate and electronic circuit apparatus using it.
  43. Feinberg Irving (Poughkeepsie NY) Wu Leon L. (Hopewell Junction NY), Thick film capacitor having very low internal inductance.

이 특허를 인용한 특허 (23)

  1. Kurt R. Odmark, Apparatus for attaching an electric coil to a printed circuit board.
  2. Wong,Chee Wai; Tay,Cheng Siew, Apparatuses and associated methods for improved solder joint reliability.
  3. Mark D. Haller, Assembly, with lead frame, for antilock brake system and associated method.
  4. Kim, Tae Jun; Song, Yoo Sun, Chip on board package for optical mice and lens cover for the same.
  5. Lin, Wen Hsiung, Circuit board having a shortage preventing structure.
  6. Knowlden, Donald Christopher; Musser, Randall Eugene; Mongold, John Allen; Faith, Chadrick Paul, Connector with secure wafer retention.
  7. Burgholzer Bruce L., Contact pin header connector repair method and repair fixture.
  8. Glasson,Richard O., Electrical cordset having connector with integral signal conditioning circuitry.
  9. Haller, Mark D., High integration electronic assembly and method.
  10. Heston, Matthew L.; Theodoras, II, James T., Method and apparatus for coupling circuit boards.
  11. Wang, Ying; Gall, Thomas P., Method and apparatus for securing a metallic substrate to a metallic housing.
  12. Rak, Stanton; Wang, Ying, Method and apparatus for securing an electrically conductive interconnect through a metallic substrate.
  13. Darr,Christopher J.; Kowtun,Peter, Method and system of electrically connecting multiple printed circuit boards.
  14. Anilkumar C. Bhatt ; David E. Houser ; John A. Welsh, Method of filling plated through holes.
  15. Wen-chou Vincent Wang ; Thomas J. Massingill ; Yasuhito Takahashi ; Lei Zhang, Modules with pins and methods for making modules with pins.
  16. Thoben, Markus; Boettcher, Richard; Buschkuehle, Marc; Rueckert, Hartwig, Power semiconductor module.
  17. Okuyama Takeshi,JPX ; Okada Akira,JPX ; Miyazawa Hideo,JPX ; Shimizu Manabu,JPX ; Sakurai Atsushi,JPX, Press-fit pin, connector and printed circuit board-connected structure.
  18. Day, Jr., James A.; Durham, Zachary B.; Remis, Luke D.; Sass, Tony C.; Sellman, Gregory D., Universal press-fit connection for printed circuit boards.
  19. Yoon, Woong K., Universal snap-fit spacer.
  20. Gregoire, George D., Wiring board construction and methods of making same.
  21. Gregoire George D., Wiring board constructions and methods of making same.
  22. Garcia, Steven E., Z-axis connection of multiple substrates by partial insertion of bulges of a pin.
  23. Budman, Mark; Chamberlin, Bruce; Li, Li; Stack, James, Zero insertion force compliant pin contact and assembly.
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