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Method of making a thin film transistor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/86
출원번호 US-0782739 (1997-01-13)
발명자 / 주소
  • Choi Jong Moon,KRX
  • Kim Jong Kwan,KRX
출원인 / 주소
  • Goldstar Electron Company, Ltd., KRX
대리인 / 주소
    Loudermilk
인용정보 피인용 횟수 : 75  인용 특허 : 11

초록

A structure and fabricating method of a thin film transistor which is suitable for an SRAM memory cell. The thin film transistor structure includes: an insulation substrate; a gate electrode formed on the insulation substrate; a gate insulation film formed on the gate electrode and on the insulation

대표청구항

[ What is claimed is:] [1.] A method for fabricating a thin film transistor comprising the steps of:forming a gate electrode having first and second sides on an insulation substrate;forming a gate insulation film on the gate electrode;forming a semiconductor layer on the gate insulation film;forming

이 특허에 인용된 특허 (11)

  1. Ishihara Hiroyasu (Tokyo JPX), Method for manufacturing a thin-film transistor operable at high voltage.
  2. Sundaresan Ravishankar (Garland TX), Method of fabricating a one-sided polysilicon thin film transistor.
  3. Batra Shubneesh (Boise ID) Manning Monte (Kuna ID), Method of forming a self-aligned low density drain inverted thin film transistor.
  4. Bracchitta John A. (South Burlington VT) Hartstein Gabriel (Burlington VT) Mongeon Stephen A. (Essex Junction VT) Speranza Anthony C. (Austin TX), Method of making a diffused lightly doped drain device with built in etch stop.
  5. Fujioka Toshio (Hamamatsu JPX), Method of making staggered gate MOSTFT.
  6. Cho Seok W. (Chungcheongbuk-do KRX) Choi Jong M. (Seoul KRX), Method of making thin film transistor with channel and drain adjacent sidewall of gate electrode.
  7. Chatterjee, Pallab K., Self-aligned stacked CMOS.
  8. Inoue Yasuo (Hyogo JPX) Nishimura Tadashi (Hyogo JPX) Ashida Motoi (Hyogo JPX), Thin film field effect element having an LDD structure.
  9. Manning Monte (Kuna ID), Thin film field effect transistor, CMOS inverter, and methods of forming thin film field effect transistors and CMOS inv.
  10. Yen Ting-Pwu (Fremont CA), Transistor fabrication methods using overlapping masks.
  11. Shepard Joseph F. (Hopewell Junction NY), Vertical dual gate thin film transistor with self-aligned gates / offset drain.

이 특허를 인용한 특허 (75)

  1. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  3. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  4. Lindert,Nick; Cea,Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
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  7. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
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  16. Shaheen,Mohamad A.; Doyle,Brian; Dutta,Suman; Chau,Robert S.; Tolchinsky,Peter, High mobility tri-gate devices and methods of fabrication.
  17. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  18. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
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  21. Datta,Suman; Brask,Justin K.; Kavalieros,Jack; Doyle,Brian S.; Dewey,Gilbert; Doczy,Mark L.; Chau,Robert S., Lateral undercut of metal gate in SOI device.
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  23. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  24. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  25. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  26. Brask,Justin K.; Doyle,Brian S.; Kavalleros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Method of forming a metal oxide dielectric.
  27. Sandhu Gurtej S. ; Batra Shubneesh ; Fazan Pierre C., Method of forming a thin film transistor.
  28. Change, Peter L. D., Method of forming a transistor having gate protection and transistor formed according to the method.
  29. Brask, Justin K.; Doyle, Brian S.; Kavalieros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material.
  30. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  31. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  32. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  33. Zhang,Yuegang; Doyle,Brian S.; Bourianoff,George I., Multi-gate carbon nano-tube transistors.
  34. Doyle, Brian S.; Datta, Suman; Jin, Been Yih; Chau, Robert, Non-planar MOS structure with a strained channel region.
  35. Doyle,Brian S.; Datta,Suman; Jin,Been Yih; Chau,Robert, Non-planar MOS structure with a strained channel region.
  36. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
  37. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
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  52. Shih, Po-Sheng, Poly-silicon thin film transistor and method for fabricating thereof.
  53. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
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  55. Chang, Peter L. D.; Doyle, Brian S., Self-aligned contacts for transistors.
  56. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
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  72. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
  73. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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