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Bonding pad structures for semiconductor integrated circuits 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/52
  • H01L-029/40
출원번호 US-0143677 (1993-10-26)
우선권정보 JP-0054223 (1989-03-07)
발명자 / 주소
  • Ichikawa Matsuo,JPX
출원인 / 주소
  • Seiko Epson Corporation, JPX
대리인 / 주소
    Johnson
인용정보 피인용 횟수 : 77  인용 특허 : 4

초록

A bonding pad structure for a semiconductor integrated circuit permits miniaturization of the bonding pad size by utilizing an opening in an overlying insulating layer to an exposed surface of an underlying multi-layer, interconnecting wiring of the integrated circuit, constituting a bonding pad for

대표청구항

[ What is claimed is:] [1.] A bonding pad structure for receiving and electrically connecting an external bonding conductor to a contact area of a circuit element formed on a substrate of a semiconductor integrated circuit, comprising:a first insulating layer patterned over the semiconductor integra

이 특허에 인용된 특허 (4)

  1. Buzzetti Franco (Monza ITX) Barbugian Natale (Milan ITX) Lombardi Paolo (Milan ITX) di Salle Enrico (Milan ITX), 6- or 7-methylenandrosta-1,4-diene-3,17-dione derivatives and process for their preparation.
  2. Morcom William R. (Melbourne Beach FL) Friedman Glenn M. (San Diego CA), Amorphous devices and interconnect system and method of fabrication.
  3. Amano Akira (Kawasaki JPX), Bump electrode structure and semiconductor chip having the same.
  4. Tsumura Kiyoaki (Itami JPX), Semiconductor device with copper wire ball bonding.

이 특허를 인용한 특허 (77)

  1. Kang, Seung H.; Krebs, Roland P.; Steiner, Kurt George; Ayukawa, Michael C.; Merchant, Sailesh Mansinh, Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures.
  2. Edgar R. Zuniga ; Samuel A. Ciani, Bonding over integrated circuits.
  3. Akram, Salman, Copper interconnect.
  4. Akram,Salman, Copper interconnect.
  5. Akram,Salman, Copper interconnect.
  6. Akram,Salman, Copper interconnect for semiconductor device.
  7. Sutardja,Sehat; Wu,Albert; Lee,Jin Yuan; Lin,Mou Shiung, Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits.
  8. Okada Takashi,JPX ; Hirano Naohiko,JPX ; Tazawa Hiroshi,JPX ; Hosomi Eiichi,JPX ; Takubo Chiaki,JPX ; Doi Kazuhide,JPX ; Hiruta Yoichi,JPX ; Shibasaki Koji,JPX, Flip-chip connection type semiconductor integrated circuit device.
  9. Kloen Hendrik K.,NLX ; Huiskamp Lodewijk P.,NLX, Integrated circuit device.
  10. Scheucher,Heimo, Integrated circuit with at least one bump.
  11. Ro Tae-Hyo,KRX ; Jeoun Ill-Hwan,KRX ; Park Byung-Suk,KRX ; Jee Yeon-Hong,KRX, Interconnect structure with a passivation layer and chip pad.
  12. Estacio, Maria Cristina B.; Tumulak, Margie, MOSFET device with multiple gate contacts offset from gate contact area and over source area.
  13. Farnworth Warren M., Mask repattern process.
  14. Farnworth Warren M., Mask repattern process.
  15. Farnworth Warren M., Mask repattern process.
  16. Farnworth Warren M., Mask repattern process.
  17. Farnworth, Warren M., Mask repattern process.
  18. Farnworth, Warren M., Mask repattern process.
  19. Warren M. Farnworth, Mask repattern process.
  20. Warren M. Farnworth, Mask repattern process.
  21. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.
  22. Pozder,Scott K.; Kobayashi,Thomas S., Method for forming a bond pad interface.
  23. Pozder, Scott K.; Kobayashi, Thomas S., Method for forming a semiconductor device having a mechanically robust pad interface.
  24. Ro, Tae-Hyo; Jeoun, Ill-Hwan; Park, Byung-Suk; Jee, Yeon-Hong, Method for manufacturing a semiconductor device.
  25. Sabin, Gregory D.; Gross, William J.; Chang, Jung-Yueh, Method for placing active circuits beneath active bonding pads.
  26. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  27. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  28. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.
  29. Kariya, Takashi; Furutani, Toshiki; Kawanishi, Takeshi, Method of manufacturing printed wiring board with component mounting pin.
  30. Lee, Jin Yuan; Chen, Ying Chih; Lin, Mou Shiung, Method of wire bonding over active area of a semiconductor circuit.
  31. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  32. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  33. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  34. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  35. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  36. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  37. Farnworth, Warren M., Methods for mask repattern process.
  38. Lin, Mou-Shiung; Ting, Tah-Kang Joseph, Methods of IC rerouting option for multiple package system applications.
  39. Lin, Mou-Shiung; Lee, Jin-Yuan; Lei, Ming-Ta; Huang, Ching-Cheng, Post passivation metal scheme for high-performance integrated circuit devices.
  40. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation method for semiconductor chip or wafer.
  41. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
  42. Kariya, Takashi; Furutani, Toshiki; Kawanishi, Takeshi, Printed board with component mounting pin.
  43. Kariya, Takashi; Furutani, Toshiki; Kawanishi, Takeshi, Printed board with component mounting pin.
  44. Kariya, Takashi; Furutani, Toshiki; Kawanishi, Takeshi, Printed wiring board with component mounting pin and electronic device using the same.
  45. Leibovitz Jacques ; Yu Park-Kee ; Zhu Ya Yun ; Cobarruviaz Maria L. ; Swindlehurst Susan J. ; Chang Cheng-Cheng ; Scholz Kenneth D., Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps.
  46. Lin, Mou Shiung; Ting, Tah Kang Joseph, Semiconductor chip with redistribution metal layer.
  47. Noriaki Fujiki JP; Takashi Yamashita JP; Shigeru Harada JP; Kazunobu Miki JP, Semiconductor device.
  48. Maeda Shigenobu,JPX, Semiconductor device and method for manufacturing the same.
  49. Maeda Shigenobu,JPX, Semiconductor device and method for manufacturing the same.
  50. Chakrabarti, Utpal Kumar; Onat, Bora M; Robinson, Kevin Cyrus; Roy, Biswanath; Wu, Ping, Semiconductor device and method of fabrication.
  51. Akram, Salman, Semiconductor device having copper interconnect for bonding.
  52. Takayoshi Andou JP; Hitoshi Ninomiya JP; Kinya Ohtani JP, Semiconductor device with the copper containing aluminum alloy bond pad on an active region.
  53. Utpal Kumar Chakrabarti ; Bora M Onat ; Kevin Cyrus Robinson ; Biswanath Roy ; Ping Wu, Semiconductor devices which utilize low K dielectrics.
  54. Bendall, R. Evan, Semiconductor pad construction enabling pre-bump probing by planarizing the post-sort pad surface.
  55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  59. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  60. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  61. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  62. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  63. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  64. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
  65. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  66. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  67. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  68. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  69. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  70. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  71. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  72. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  73. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  74. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  75. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  76. Lin,Mou Shiung, Top layers of metal for high performance IC's.
  77. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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