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Method and apparatus for dynamic conversion of computer instructions 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/45
출원번호 US-0703804 (1996-08-27)
발명자 / 주소
  • Ebcioglu Mahmut Kemal
  • Groves Randall Dean
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Bailey
인용정보 피인용 횟수 : 97  인용 특허 : 0

초록

An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache

대표청구항

[ We claim:] [1.] A method of executing a computer program, compiled for sequential instruction execution, on a parallel instruction processing system, the method comprising the steps of:retrieving, in response to a cache miss, a group of sequential instructions having a first and second conditional

이 특허를 인용한 특허 (97)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  11. Mohamed,Moataz A.; Spence,John R., Apparatus and method for an improved performance VLIW processor.
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  17. McGuire, Morgan S.; Demetriou, Christopher G.; Grant, Brian K.; Papakipos, Matthew N., Application program interface of a parallel-processing computer system that supports multiple programming languages.
  18. McGuire, Morgan S.; Demetriou, Christopher G.; Grant, Brian K.; Papakipos, Matthew N., Application program interface of a parallel-processing computer system that supports multiple programming languages.
  19. Shail Aditya Gupta ; B. Ramakrishna Rau ; Richard C. Johnson ; Michael S. Schlansker, Automatic design of VLIW instruction formats.
  20. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  21. Jacobs, Eino; Ang, Michael, Compressed instruction format for use in a VLIW processor.
  22. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  23. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  24. Greenhalgh, Peter Richard; Hill, Stephen John, Data processing apparatus and method for identifying sequences of instructions.
  25. Charnell,William Thomas; Plummer,Wayne; Darnell,Stephen; Dias,Blaise Abel Alec; Guthrie,Philippa Joy; Kramskoy,Jeremy Paul; Sexton,Jeremy James; Wynn,Michael John; Rautenbach,Keith; Thomas,Stephen Pa, Direct invocation of methods using class loader.
  26. Djafarian, Karim; Laurenti, Gilbert; Catan, Herve; Gillet, Vincent, Dual access instruction and compound memory access instruction with compatible address fields.
  27. Kramskoy,Jeremy Paul; Charnell,William Thomas; Darnell,Stephen; Dias,Blaise Abel Alec; Guthrie,Philippa Joy; Plummer,Wayne; Sexton,Jeremy James; Wynn,Michael John; Rautenback,Keith; Thomas,Stephen Pa, Dynamic compiler and method of compiling code to generate dominant path and to handle exceptions.
  28. Carlough, Steven R.; Haess, Juergen; Kroener, Michael K.; Mueller, Silvia M., Dynamic hardware trace supporting multiphase operations.
  29. Campbell,John E.; Devine,William T.; Ventrone,Sebastian T., Dynamic object-level code transaction for improved performance of a computer.
  30. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
  31. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
  32. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  33. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
  34. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  35. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  36. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  37. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  38. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  39. Darnell, Stephen; Charnell, William Thomas; Plummer, Wayne; Dias, Blaise Abel Alec; Guthrie, Philippa Joy; Kramskoy, Jeremy Paul; Sexton, Jeremy James; Wynn, Michael John; Rautenback, Keith; Thomas, , Hash table dispatch mechanism for interface methods.
  40. Kramskoy, Jeremy Paul, Inter-method control transfer for execution engines with memory constraints.
  41. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  42. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  43. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  44. Thomas, Stephen Paul; Charnell, William Thomas; Darnell, Stephen; Dias, Blaise Abel Alec; Guthrie, Philippa Joy; Kramskoy, Jeremy Paul; Sexton, Jeremy James; Wynn, Michael John; Rautenback, Keith; Pl, Low-contention grey object sets for concurrent, marking garbage collection.
  45. Nguyen,Hung; Wichman,Shannon, Marking queue for simultaneous execution of instructions in code block specified by conditional execution instruction.
  46. Eidt Erik L., Method and apparatus for optimizing interface dispatching in an object-oriented programming environment.
  47. Sakhin Yuli Kh.,RUX ; Artyomov Alexander M.,RUX ; Lizorkin Alexey P.,RUX ; Rudometov Vladimir V.,RUX ; Nazarov Leonid N.,RUX, Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to.
  48. Raje Prasad A. ; Siu Stuart C., Method and apparatus for sequencing and decoding variable length instructions with an instruction boundary marker with.
  49. Faraboschi Paolo ; Fisher Joseph A., Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition.
  50. Rautenback,Keith; Charnell,William Thomas; Darnell,Stephen; Dias,Blaise Abel Alec; Guthrie,Philippa Joy; Kramskoy,Jeremy Paul; Sexton,Jeremy James; Wynn,Michael John; Plummer,Wayne; Thomas,Stephen Pa, Method and structure for reducing search times.
  51. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  52. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  53. Thomas, Stephen Paul; Charnell, William Thomas; Darnell, Stephen; Dias, Blaise Abel Alec; Guthrie, Philippa Joy; Kramskoy, Jeremy Paul; Sexton, Jeremy James; Wynn, Michael John; Rautenbach, Keith; Plummer, Wayne, Method and system for dynamic memory management.
  54. Thomas, Stephen Paul; Charnell, William Thomas; Darnell, Stephen; Dias, Blaise Abel Alec; Guthrie, Philippa Joy; Kramskoy, Jeremy Paul; Sexton, Jeremy James; Wynn, Michael John; Rautenbach, Keith; Plummer, Wayne, Method and system for dynamic memory management.
  55. Plummer,Wayne; Charnell,William Thomas; Darnell,Stephen; Dias,Blaise Abel Alec; Guthrie,Philippa Joy; Kramskoy,Jeremy Paul; Sexton,Jeremy James; Wynn,Michael John; Rautenback,Keith; Thomas,Stephen Pa, Method and system for handling device driver interrupts.
  56. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  57. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  58. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  59. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  60. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  61. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  62. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  63. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  64. Kramskoy, Jeremy Paul; Charnell, William Thomas; Darnell, Stephen; Dias, Blaise Abel Alec; Guthrie, Philippa Joy; Plummer, Wayne; Sexton, Jeremy James; Wynn, Michael John; Rautenbach, Keith; Thomas, , Method and system of cache management using spatial separation of outliers.
  65. Charnell, William Thomas; Plummer, Wayne; Darnell, Stephen; Dias, Blaise Abel Alec; Guthrie, Philippa Joy; Kramskoy, Jeremy Paul; Sexton, Jeremy James; Wynn, Michael John; Rautenback, Keith; Thomas, , Method and system of memory management using stack walking.
  66. Guthrie, Philippa Joy; Charnell, William Thomas; Darnell, Stephen; Dias, Blaise Abel Alec; Plummer, Wayne; Kramskoy, Jeremy Paul; Sexton, Jeremy James; Wynn, Michael John; Rautenback, Keith; Thomas, , Method and system of testing and verifying computer code in a multi-threaded environment.
  67. Tserng,Christopher, Method for scheduling processors and coprocessors with bit-masking.
  68. Hoogerbrugge, Jan; Augusteijn, Alexander, Method of executing an interpreter program.
  69. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  70. Agarwal, Rakesh; Baltaretu, Oana, Methods for improved simulation of integrated circuit designs.
  71. Papakipos, Matthew N.; Demetriou, Christopher G., Multi-thread runtime system.
  72. Charnell,William Thomas; Plummer,Wayne; Darnell,Stephen; Dias,Blaise Abel Alec; Guthrie,Philippa Joy; Kramskoy,Jeremy Paul; Sexton,Jeremy James; Wynn,Michael John; Rautenbach,Keith; Thomas,Stephen Pa, Multi-threaded fragment patching.
  73. Moreno Jaime Humberto, Object-code compatible representation of very long instruction word programs.
  74. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  75. Ziegler, Michael L., Program control flow conditioned on presence of requested data in cache memory.
  76. Barry, Edwin Franklin; Pechanek, Gerald George; Marchand, Patrick R., Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor.
  77. Edwin F. Barry ; Gerald G. Pechanek ; Patrick R. Marchand, Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor.
  78. Papakipos, Matthew N.; Demetriou, Christopher G.; Tuck, Nathan D.; Grant, Brian K., Runtime system for executing an application in a parallel-processing computer system.
  79. Nguyen,Hung; Wichman,Shannon, Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction groups.
  80. Master,Paul L.; Watson,John, Storage and delivery of device features.
  81. Isaman, David L., Symbolic store-load bypass.
  82. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  83. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  84. Demetriou, Christopher G.; Papakipos, Matthew N., Systems and methods for caching compute kernels for an application running on a parallel-processing computer system.
  85. Papakipos, Matthew N.; Grant, Brian K.; Demetriou, Christopher G.; McGuire, Morgan S., Systems and methods for compiling an application for a parallel-processing computer system.
  86. Demetriou, Christopher G.; Papakipos, Matthew N.; Gibbs, Noah L., Systems and methods for debugging an application running on a parallel-processing computer system.
  87. Papakipos, Matthew N.; Grant, Brian K.; McGuire, Morgan S.; Demetriou, Christopher G., Systems and methods for determining compute kernels for an application in a parallel-processing computer system.
  88. Crutchfield, William Y.; Grant, Brian K.; Papakipos, Matthew N., Systems and methods for dynamically choosing a processing element for a compute kernel.
  89. Papakipos, Matthew N.; Grant, Brian K.; Demetriou, Christopher G, Systems and methods for generating reference results using a parallel-processing computer system.
  90. Papakipos, Matthew N.; Grant, Brian K.; Demetriou, Christopher G, Systems and methods for generating reference results using parallel-processing computer system.
  91. Tuck, Nathan D.; Papakipos, Matthew N.; Grant, Brian K.; Demetriou, Christopher G.; Civlin, Jan, Systems and methods for profiling an application running on a parallel-processing computer system.
  92. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
  93. Arnon, Dan; Meiri, David, Techniques for dynamic binding of device identifiers to data storage devices.
  94. Torvalds, Linus; Bedichek, Robert; Johnson, Stephen, Translating instructions in a speculative processor.
  95. Mahalingaiah Rupaka, Using ECC/parity bits to store predecode information.
  96. Zuraski, Jr., Gerald D., Using type bits to track storage of ECC and predecode bits in a level two cache.
  97. Jacobs Eino ; Ang Michael, VLIW processor which processes compressed instruction format.
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