|국가/구분||United States(US) Patent 등록|
|미국특허분류(USC)||395/379 ; 395/706 ; 395/391 ; 395/392|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 97 인용 특허 : 0|
An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary dependin...
[ We claim:] [1.] A method of executing a computer program, compiled for sequential instruction execution, on a parallel instruction processing system, the method comprising the steps of:retrieving, in response to a cache miss, a group of sequential instructions having a first and second conditional branch instruction, and first and second instructions that are dependent upon the first and second conditional branch instructions, respectively;creating a compound instruction for parallel execution including the steps of:inserting, for each of the first and...