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Structure for fabricating a bonding pad having improved adhesion to an underlying structure 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/00
출원번호 US-0409784 (1995-03-24)
발명자 / 주소
  • Lien Chuen-Der
출원인 / 주소
  • Integrated Device Technology, Inc.
대리인 / 주소
    Skjerven, Morrill, MacPherson, Franklin & Friel
인용정보 피인용 횟수 : 34  인용 특허 : 0

초록

An insulating layer having an irregular upper surface is provided to improve the adhesion and increase the coefficient of friction between the insulating layer and a bonding pad formed over the insulating layer. By making the upper surface of the insulating layer irregular, the area of contact betwe

대표청구항

[ I claim:] [1.] An integrated circuit structure comprising:a semiconductor substrate;a first electrically insulating layer situated over the semiconductor substrate, wherein the first insulating layer has one or more cavities which extend into the first insulating layer from an upper surface of the

이 특허를 인용한 특허 (34)

  1. Lee, Ellis; Huang, Yimin; Yew, Tri-Rung, Bonding pad structure.
  2. Chan Chin-Jong,TWX ; Chung Hsiu-Hsin,TWX ; Lin Rueyway,TWX, Bonding pad structure for integrated circuit (I).
  3. Takeuchi,Masanori, Flexible wiring board, an intermediate product of a flexible wiring board, and a multi-layer flexible wiring board.
  4. Eldridge, Benjamin N.; Mathieu, Gaetan, Interconnect assemblies and methods.
  5. Santangelo, Antonello; Cascino, Salvatore; Gervasi, Leonardo, Lateral MOS device with minimization of parasitic elements.
  6. Strandberg Jan I. ; Chazan David J. ; Skinner Michael P., Low-impedance high-density deposited-on-laminate structures having reduced stress.
  7. Lee,Jin Hyuk; Kim,Gu Sung; Lee,Dong Ho; Jang,Dong Hyeon, Method for manufacturing a wafer level chip scale package.
  8. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  9. Okabe Shuhichi,JPX ; Sakurai Keizo,JPX, Multilayer printed circuit board having a concave metal portion.
  10. Sutardja, Sehat, Patterns of passivation material on bond pads and methods of manufacture thereof.
  11. Tomimori, Hiroaki; Aoki, Hidemitsu; Mikagi, Kaoru; Furuya, Akira; Tao, Tetsuya, Process for making a semiconductor device having a roughened surface.
  12. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads.
  13. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads.
  14. Song, Young-Hee; Choi, Il-Heung; Kim, Jeong-Jin; Sohn, Hae-Jeong; Lee, Chung-Woo, Semiconductor chip having bond pads.
  15. Song,Young Hee; Choi,Il Heung; Kim,Jeong Jin; Sohn,Hae Jeong; Lee,Chung Woo, Semiconductor chip having bond pads.
  16. Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads and multi-chip package.
  17. Song, Young-Hee; Choi, Il-Heung; Kim, Jeong-Jin; Sohn, Hae-Jeong; Lee, Chung-Woo, Semiconductor chip having bond pads and multi-chip package.
  18. Noriaki Fujiki JP; Takashi Yamashita JP; Shigeru Harada JP; Kazunobu Miki JP, Semiconductor device.
  19. Watanabe, Kenichi; Ikeda, Masanobu; Kimura, Takahiro, Semiconductor device and method for manufacturing the same.
  20. Watanabe, Kenichi; Ikeda, Masanobu; Kimura, Takahiro, Semiconductor device and method for manufacturing the same.
  21. Watanabe, Kenichi; Ikeda, Masanobu; Kimura, Takahiro, Semiconductor device and method for manufacturing the same.
  22. Shinogi, Hiroyuki; Taniguchi, Toshimitsu, Semiconductor device and the manufacturing method thereof.
  23. Kim, Shin; Chung, Tae-Gyeong; Kim, Nam-Seog; Lee, Woo-Dong; Lee, Jin-Hyuk, Semiconductor device bonding pad resistant to stress and method of fabricating the same.
  24. Tomimori,Hiroaki; Aoki,Hidemitsu; Mikagi,Kaoru; Furuya,Akira; Tao,Tetsuya, Semiconductor device having a roughened surface.
  25. Song,Young Hee; Choi,Il Heung; Kim,Jeong Jin; Sohn,Hae Jeong; Lee,Chung Woo, Semiconductor multi-chip package.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  31. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  32. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  33. Eldridge,Benjamin N.; Mathieu,Gaetan, Variable width resilient conductive contact structures.
  34. Behrens, Jörg, Wire-bonded semiconductor component with reinforced inner connection metallization.
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