초록 ▼

A multiport register file memory includes a cross-coupled sense amplifier as a storage element. A buffered switching circuit provides a voltage potential to the storage element in response to a write enable signal for switching-on/off the storage element. Each storage element provides two storage no

A multiport register file memory includes a cross-coupled sense amplifier as a storage element. A buffered switching circuit provides a voltage potential to the storage element in response to a write enable signal for switching-on/off the storage element. Each storage element provides two storage nodes which are coupled to corresponding switched bit lines. Coupling between each storage node and corresponding switched bit lines is provided by a pass transistor that is controlled by a word line attached to a gate of the pass transistor. The write operation begins by powering-off at least one controlled supply voltage rail that provides a voltage potential to the storage element. A small voltage swing of between two hundred and five hundred millivolts (200-500 mV) is supplied from the bit lines to the storage nodes of the sense amplifier through the pass transistors. The cross-coupled sense amplifier is then switched on by connecting the sense amplifier to the supply voltage node previously switched-off by the buffered switching circuit. Switching on the sense amplifier results in the amplification of the small voltage swing and storage of the resulting signal. The storage nodes are then accessed by using word lines to activate corresponding pass transistors capable of passing small or large voltage swing signals held by the storage element.

대표청구항 ▼

[ What is claimed is:] [1.] A multiport register file comprising:a storage element having first and second storage nodes, a positive voltage supply node, and a negative voltage supply node;a plurality of first switched bit lines coupled to said first storage node and a plurality of second switched b

[ What is claimed is:] [1.] A multiport register file comprising:a storage element having first and second storage nodes, a positive voltage supply node, and a negative voltage supply node;a plurality of first switched bit lines coupled to said first storage node and a plurality of second switched bit lines coupled to said second storage node; anda first buffered switching circuit coupled to said negative voltage supply node of said storage element, said first buffered switching circuit for switching-on/off said storage element, wherein during a write operation said storage element is switched-off, and a small voltage swing of between about 0.2 and about 0.5 volts is placed on said first and second storage nodes from selected first and second switched bit lines, and, during a read operation said storage element amplifies said small voltage swing of between about 0.2 and about 0.5 volts to provide an amplified signal when said storage element is switched on.