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System and method for diallocating stream from a stream buffer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/02
출원번호 US-0519032 (1995-08-24)
발명자 / 주소
  • Mayfield Michael John
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Kordzik
인용정보 피인용 횟수 : 86  인용 특허 : 14

초록

A system and method to use stream filters to defer deallocation of a stream based on the activity level of the stream, thereby preventing a stream thrashing situation from occurring. The least recently used ("LRU") stream is deallocated only after a number of potential new streams are detected. In a

대표청구항

[ What is claimed is:] [1.] An apparatus operable for prefetching data to a memory subsystem from a main memory, wherein said memory subsystem is associated with a processor coupled to said main memory, said apparatus comprising:a stream buffer operable for containing X streams, wherein X is a posit

이 특허에 인용된 특허 (14)

  1. Tran Thang (Austin TX), Combination prefetch buffer and instruction cache.
  2. Kass William J. (Easley SC), Computer apparatus including a main memory prefetch cache and method of operation thereof.
  3. Jouppi Norman P. (Palo Alto CA), Data processing system and method with prefetch buffers.
  4. Goodwin Paul M. (Littleton MA) Thaller Kurt M. (Acton MA) Maskas Barry A. (Sterling MA), History buffer control to reduce unnecessary allocations in a memory stream buffer.
  5. Hall William E. (Portland OR), Instruction cache memory system.
  6. Westberg Thomas E. (Sudbury MA), Intelligent cache memory and prefetch method based on CPU data fetching characteristics.
  7. Tatosian David A. (Stow MA) Goodwin Paul M. (Littleton MA) Thaller Kurt M. (Acton MA) Smelser Donald W. (Bolton MA), Memory stream buffer.
  8. Touch Joseph D. (Willingboro NJ) Farber David J. (Landenberg PA), Memory-side driven anticipatory instruction transfer interface with processor-side instruction selection.
  9. Goodwin Paul M. (Littleton MA) Thaller Kurt M. (Acton MA), Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffe.
  10. Zangenehpour Saied (Stevensville MI), Method of varying the amount of data prefetched to a cache memory in dependence on the history of data requests.
  11. Chi Chi-Hung (Croton-on-Hudson NY), Multilevel instruction cache.
  12. Miura Shuuichi (313 Izumigamoriryo ; 20-1 ; Mizukicho 2-chome Hitachi-shi ; Ibaraki-ken JPX) Kurosawa Kenichi (22-2 ; Mikanoharacho 2-chome Hitachi-shi ; Ibaraki-ken JPX) Nakamikawa Tetsuaki (17-1-40, Prefetch buffer and information processing system using the same.
  13. Liu Lishing (Pleasantville NY), Sequential prefetching with deconfirmation.
  14. Goodwin Paul M. (Littleton MA) Smelser Donald (Bolton MA) Tatosian David A. (Stow MA), Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetchi.

이 특허를 인용한 특허 (86)

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