초록 ▼

Apparatus and method for emulating a circuit having at least one multiport RAM that requires at least two programmable device to be emulated. The multiport RAM has an array of storage elements, a read multiplexer, and a write multiplexer and is partitioned into a number of slices, each of which is c

Apparatus and method for emulating a circuit having at least one multiport RAM that requires at least two programmable device to be emulated. The multiport RAM has an array of storage elements, a read multiplexer, and a write multiplexer and is partitioned into a number of slices, each of which is capable of being programmed into one of an array of programmable devices. In one embodiment, each slice is another multiport RAM having the same depth, number of read ports, and number of write ports as the multiport RAM being emulated, but having a narrower width than the multiport RAM being emulated. In another embodiment, the multiport RAM is partitioned into read slices and write slices, which will typically be of different widths. The read slices comprise the read multiplexers. The write slices comprise the array of storage elements and the write multiplexers.

대표청구항 ▼

[ I claim:] [1.] An emulation system for emulating a circuit having at least one multiport RAM that requires at least two programmable devices to be emulated, comprising:(a) a plurality of programmable devices;(b) a configuration unit electrically coupled to said plurality of programmable devices fo

[ I claim:] [1.] An emulation system for emulating a circuit having at least one multiport RAM that requires at least two programmable devices to be emulated, comprising:(a) a plurality of programmable devices;(b) a configuration unit electrically coupled to said plurality of programmable devices for programming said plurality of programmable devices to emulate the circuit; and(c) a partition unit coupled to said configuration unit for partitioning the at least one multiport RAM into at least two circuit portions, the at least two circuit portions capable of being programmed into two of said programmable devices by said configuration unit, and wherein during emulation there are no logical data flow paths between the at least two circuit portions; andwherein the at least two circuit portions each comprise another multiport RAM having the same depth, number of read ports, and number of write ports as the at least one multiport RAM, but having a narrower width than the at least one multiport RAM.