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Digital signal driver circuit having a high slew rate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-017/16
  • H03K-017/04
  • H03K-019/003
출원번호 US-0551221 (1995-10-31)
발명자 / 주소
  • Rawson William Peter
출원인 / 주소
  • Hewlett-Packard Co.
인용정보 피인용 횟수 : 35  인용 특허 : 9

초록

A driver circuit for driving multiple lines with unknown loads uses a high slew rate driver to drive the output during input signal transitions, and uses a termination driver to drive the output during input signal steady state conditions. The high slew rate driver provides rapid transitions, and th

대표청구항

[ I claim:] [1.] A driver circuit having a circuit input and a circuit output for driving a digital input signal to an unknown load comprising:a high slew rate driver connected to the circuit output for driving an output signal based on the input signal during input signal transitions between states

이 특허에 인용된 특허 (9)

  1. Van Lehn David A. (Houston TX) Flaherty Edward H. (Houston TX), CMOS output buffer having improved noise characteristics.
  2. Boler Clifford H. (Bloomington MN) Leake William W. (St. Paul MN) Rai Surinder S. (Plymouth MN) Zemske Gene B. (Minneapolis MN), CMOS output buffer providing high drive current with minimum output signal distortion.
  3. Kano Toshiyuki (Tokyo JPX), Drive circuit comprising a subsidiary drive circuit.
  4. Prater James S. (Fort Collins CO), Driver circuit providing load and time adaptive current.
  5. Bianchi Christopher C. (Havertown PA), Interface circuits including driver circuits with switching noise reduction.
  6. Aoki Kazuo (Itami) Shichinohe Daisuke (Itami JPX), MOS transistor output circuit.
  7. Tanaka Fuminari (Tokyo JPX) Nonaka Satoshi (Tokyo JPX), Output circuit for CMOS integrated circuit with pre-buffer to reduce distortion of output signal.
  8. Bathaee Mehdi (Riverside CA), Output driver for reducing transient noise in integrated circuits.
  9. Tanaka Yasunori (Yokohama JPX), Slew-rate limited output driver having reduced switching noise.

이 특허를 인용한 특허 (35)

  1. Pitkethly, Scott; Masleid, Robert Paul, Advanced repeater utilizing signal distribution delay.
  2. Pitkethly,Scott; Masleid,Robert Paul, Advanced repeater utilizing signal distribution delay.
  3. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  4. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  5. Pitkethly, Scott, Advanced repeater with duty cycle adjustment.
  6. Masleid, Robert Paul; Dholabhai, Vatsal, Circuit with enhanced mode and normal mode.
  7. Masleid, Robert Paul; Kowalczyk, Andre, Circuits and methods for detecting and assisting wire transitions.
  8. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  9. Masleid,Robert Paul; Kowalczyk,Andre, Circuits and methods for detecting and assisting wire transitions.
  10. Masleid, Robert Paul, Column select multiplexer circuit for a domino random access memory array.
  11. Masleid, Robert Paul, Configurable delay chain with stacked inverter delay elements.
  12. Masleid, Robert Paul, Configurable delay chain with switching control for tail delay elements.
  13. Masleid, Robert Paul, Configurable tapered delay chain with multiple sizes of delay elements.
  14. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  15. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  16. Masleid, Robert P.; Pitkethly, Scott, Cross point switch.
  17. Hunt, Kenneth S., Increasing drive strength and reducing propagation delays through the use of feedback.
  18. De Geeter, Bart; Furrer, Nicolas, Inductive load driver slew rate controller.
  19. De Geeter, Bart; Furrer, Nicolas, Inductive load driver slew rate controller.
  20. Masleid, Robert P, Inverting zipper repeater circuit.
  21. Masleid, Robert P., Inverting zipper repeater circuit.
  22. Masleid, Robert Paul, Inverting zipper repeater circuit.
  23. Masleid, Robert, Leakage efficient anti-glitch filter.
  24. Shi Xudong, Low power CMOS line driver with dynamic biasing.
  25. Masleid, Robert Paul, Power efficient multiplexer.
  26. Masleid, Robert Paul, Power efficient multiplexer.
  27. Masleid, Robert Paul, Power efficient multiplexer.
  28. Masleid, Robert Paul, Power efficient multiplexer.
  29. Masleid,Robert Paul, Power efficient multiplexer.
  30. Masleid, Robert Paul; Dholabhai, Vatsal; Klingner, Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  31. Masleid,Robert Paul; Dholabhai,Vatsal; Klingner,Christian, Repeater circuit having different operating and reset voltage ranges, and methods thereof.
  32. Masleid, Robert Paul; Dholabhai, Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  33. Masleid,Robert Paul; Dholabhai,Vatsal, Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability.
  34. Masleid, Robert P.; Burr, James B., Stacked inverter delay chain.
  35. Masleid,Robert P.; Burr,James B., Stacked inverter delay chain.
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