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Real time switch overs from one set of timing signals to a redundant set of timing signals in an ATM system, as required by periodic maintenance checks, are accomplished without incurring data errors by this apparatus and method. Each switch over apparatus has a phase locked loop with a controlled c

Real time switch overs from one set of timing signals to a redundant set of timing signals in an ATM system, as required by periodic maintenance checks, are accomplished without incurring data errors by this apparatus and method. Each switch over apparatus has a phase locked loop with a controlled control loop which assists the phase locked loop in rapidly achieving nearly perfect phase locks to one of multiple system reference clocks. The characteristics of the special phased locked loop provide the stability and the timing functions necessary for switch overs between reference clocks to produce errorless ATM signal handling.

대표청구항 ▼

[ I claim:] [1.] An apparatus for switching between a plurality sets of data pulse trains without incurring a data error, comprising:a multiplexer for selecting one set of pulse trains from the plurality of pulse train sets to be connected to a set of multiplexer output terminals, said selected set

[ I claim:] [1.] An apparatus for switching between a plurality sets of data pulse trains without incurring a data error, comprising:a multiplexer for selecting one set of pulse trains from the plurality of pulse train sets to be connected to a set of multiplexer output terminals, said selected set of pulse trains including a clock pulse train and a synchronization pulse train which are delivered to a clock output terminal and a synchronization output terminal, respectively;a first pulse dropping means for selectively dropping at least one pulse of the selected clock pulse train having an input connected to said clock output terminal and an output terminal;a phase detector having a first input connected to said output of said first pulse dropping means, a second input and an output;a filter having an input connected to said output of said phase detector and an output;a controlled oscillator having a control input connected to said output of said filter and an outputa divide by N means connected to said output of said controlled oscillator for providing at an output thereof a pulse very similar to one of the pulses of said controlled oscillator for every N pulses of said controlled oscillator, where N is an integer,a second pulse dropping means having a clock input connected to said controlled oscillator output, a control input and an output which is connected to said second input of said phase detector; anda pulse aligner having a first input connected to said output of said divided by N means, a second input connected to said synchronization output terminal of said multiplexer, a first output connected to said first pulse dropping means and a second output connected to said second pulse dropping means,said pulse aligner senses the difference between said synchronization pulse train from said multiplexer and said output of said divide by N means and controls said first and second pulse dropping means to drop pulses from their respective trains to drive said phase detector to control said oscillator to reduce the difference sensed by said pulse aligner until said difference is very small, upon reaching said very small difference sensed by said pulse aligner, said first and second pulse dropping means are disabled and become essentially closed switches allowing said phase detector to drive said controlled oscillator in typical phase locked loop operation.