이 특허를 인용한 특허 (60)

1. Keshavram N. Murty ; Nazar A. Zaidi, Apparatus and method for detecting and handling self-modifying code conflicts in an instruction fetch pipeline.

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2. Irie,Naohiko; Werner,Tony Lee, Branch control memory.

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3. Puzak, Thomas R.; Hartstein, Allan M.; Charney, Mark; Prener, Daniel A.; Oden, Peter H.; Srinivasan, Vijayalakshmi, Branch history guided instruction/data prefetching.

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4. Sivaram Krishnan ; Sebastian Haviuj Ziesler, Branch instruction mechanism for processor.

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5. Jung, Yong-Kyu, Branch look-ahead system apparatus and method for branch look-ahead microprocessors.

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6. Krishnan Sivaram ; Ziesler Sebastian Haviuj, Branch prediction and target instruction control for processor.

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7. Emma, Philip G.; Hartstein, Allan M.; Langston, Keith N.; Prasky, Brian R.; Puzak, Thomas R.; Webb, Charles F., Branch prediction instructions having mask values involving unloading and loading branch history data.

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8. Bonanno, James J.; Mitran, Marcel; Prasky, Brian R.; Siu, Joran; Slegel, Timothy J.; Vasilevskiy, Alexander, Branch prediction preloading.

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9. Bonanno, James J.; Mitran, Marcel; Prasky, Brian R.; Siu, Joran; Slegel, Timothy J.; Vasilevskiy, Alexander, Branch prediction preloading.

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10. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Cache allocation policy based on speculative request history.

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11. Chheda, Saurabh; Carver, Kristopher; Ashok, Raksit, Energy-focused compiler-assisted branch prediction.

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12. Chheda, Saurabh; Carver, Kristopher; Ashok, Raksit, Energy-focused compiler-assisted branch prediction.

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13. Chheda, Saurabh; Carver, Kristopher; Ashok, Raksit, Energy-focused compiler-assisted branch prediction.

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14. Chheda, Saurabh; Carver, Kristopher; Ashok, Raksit, Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control.

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15. Chheda, Saurabh; Carver, Kristopher; Ashok, Raksit, Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control.

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16. Emma, Philip G.; Hartstein, Allan M.; Prasky, Brian R.; Puzak, Thomas R.; Srinivasan, Vijayalakshmi, Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history.

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17. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Extended cache state with prefetched stream ID information.

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18. Gilad, Zvika; Khait, Semion, In vivo device with flexible circuit board and method for assembly thereof.

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19. Avni, Dov, In vivo sensing device with a circuit board having rigid sections and flexible sections.

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20. Naohiko Irle ; Tony Lee Werner, Indexing branch target instruction memory using target address generated by branch control instruction to reduce branch latency.

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21. Bonanno, James J.; Collura, Adam B.; Mayer, Ulrich; Prasky, Brian R.; Saporito, Anthony; Shum, Chung-Lung K., Instruction filtering.

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22. Bonanno, James J.; Collura, Adam B.; Mayer, Ulrich; Prasky, Brian R.; Saporito, Anthony; Shum, Chung-Lung K., Instruction filtering.

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23. Sharangpani Harshvardhan ; Corwin Michael Paul ; Morris Dale ; Fielden Kent ; Yeh Tse-Yu ; Mulder Hans ; Hull James, Instruction template for efficient processing clustered branch instructions.

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24. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions.

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25. Stavrou, Kyriakos A.; Gibert Codina, Enric; Codina, Josep M.; Gomez Requena, Crispin; Gonzalez, Antonio; Hyuseinova, Mirem; Kotselidis, Christos E.; Latorre, Fernando; Lopez, Pedro; Lupon, Marc; Madriles Gimeno, Carlos; Magklis, Grigorios; Marcuello, Pedro; Martinez Vicente, Alejandro; Martinez, Raul; Ortega, Daniel; Pavlou, Demos; Tournavitis, Georgios; Xekalakis, Polychronis, Managed instruction cache prefetching.

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26. Arimilli, Ravi Kumar; Arimilli, Lakshminarayana Baba; Clark, Leo James; Dodson, John Steven; Guthrie, Guy Lynn; Fields, Jr., James Stephen, Mechanism for high performance transfer of speculative request data between levels of cache hierarchy.

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27. Thompson, Carol L.; Zi gler, Michael L.; Huck, Jerome C.; Dwyer, Lawrence D. K. B., Method and apparatus for enabling a compiler to reduce cache misses by performing pre-fetches in the event of context switch.

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28. Raz Yoav ; Blumenau Steven M., Method and apparatus for performing a modified prefetch which sends a list identifying a plurality of data blocks.

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29. Serocki Steven ; Holler Anne Marie, Method and apparatus for reduction of indirect branch instruction overhead through use of target address hints.

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30. Holmberg Per,SEX, Method and system for branch prediction.

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31. Levine Frank Eliot ; Starke William John ; Welbon Edward Hugh ; Randolph Jack Chris, Method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring.

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32. Stringer,Lynd M., Method and system for scheduling software pipelined loops.

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33. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Method for instruction extensions for a tightly coupled speculative request unit.

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34. Sharangpani, Harshvardhan; Yeh, Tse-Yu; Corwin, Michael Paul; Mittal, Millind; Fielden, Kent G.; Morris, Dale; Gupta, Rajiv; Schlansker, Michael; Poplingher, Mircea, Method for processing branch operations.

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35. Yasue, Masahiro; Hatakeyama, Akiyuki, Methods and apparatus for dynamic prediction by software.

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36. Yasue, Masahiro; Hatakeyama, Akiyuki, Methods and apparatus for dynamic prediction by software.

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37. Poplingher, Mitchell Alexander; Yeh, Tse-Yu, Microprocessor having a branch predictor using speculative branch registers.

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38. Elwood, Matthew Paul; Butcher, David John; Grisenthwaite, Richard Roy, Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding.

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39. Ravi Kumar Arimilli ; Lakshminarayana Baba Arimilli ; Leo James Clark ; John Steven Dodson ; Guy Lynn Guthrie ; James Stephen Fields, Jr., Optimized cache allocation algorithm for multiple speculative requests.

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40. Krishnan, Sivaram; Zlesler, Sebastian Havluj, Pipelined processor executing logical or mathematical operation specifying compare folded branch instruction.

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41. Gonion, Jeffry E., Predicting a result for an actual instruction when processing vector instructions.

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42. Gonion, Jeffry E., Predicting a result of a dependency-checking instruction when processing vector instructions.

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43. Morris, Dale C.; Callister, James R.; Undy, Stephen R., Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted.

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44. Wang, Hong; Kling, Ralph; Grochowski, Edward T.; Ramakrishnan, Kalpana, Presbyopic branch target prefetch method and apparatus.

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45. Wang, Hong; Kling, Ralph; Grochowski, Edward T.; Ramakrishnan, Kalpana, Presbyopic branch target prefetch method and apparatus.

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46. Corwin Michael P. ; Yeh Tse-Yu ; Poplingher Mircea ; Scafidi Carl C., Processor and instruction set with predict instructions.

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47. Freeman Jackie Andrew, Programmable branch prediction system and method for inserting prediction operation which is independent of execution o.

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48. Morris, Dale; McCormick, James E., Run-time updating of prediction hint instructions.

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49. Moritz, Csaba Andras; Chheda, Saurabh; Carver, Kristopher, Securing microprocessors against information leakage and physical tampering.

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50. Moritz, Csaba Andras; Chheda, Saurabh; Carver, Kristopher, Securing microprocessors against information leakage and physical tampering.

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51. Chheda, Saurabh; Carver, Kristopher; Ashok, Raksit, Security of program executables and microprocessors based on compiler-architecture interaction.

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52. Moritz, Csaba Andras, Statically speculative compilation and execution.

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53. Moritz, Csaba Andras, Statically speculative compilation and execution.

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54. Moritz,Csaba Andras, Statically speculative compilation and execution.

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55. Sharangpani Harshvardhan ; Fielden Kent, Storing predicted branch target address in different storage according to importance hint in branch prediction instruction.

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56. Wichman,Shannon A.; Kalluri,Seshagiri Prasad, System and method for executing software program instructions using a condition specified within a conditional execution instruction.

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57. Arimilli, Ravi Kumar; Arimilli, Lakshminarayana Baba; Clark, Leo James; Dodson, John Steven; Guthrie, Guy Lynn; Fields, Jr., James Stephen, Time based mechanism for cached speculative data deallocation.

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58. Krick Robert Franklin ; Lee Chan Woo ; D'Sa Reynold Viriato, Trace branch prediction unit.

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59. O'Dowd,Anthony John, Tracing the execution path of a computer program.

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60. Sivaram Krishnan ; Sebastian Havluj Ziesler, Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions.

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