초록 ▼

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a programmed instruction providing an on chip

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable instruction set accelerator RISA. The programmable execution units may be made using a field programmable gate array having a configuration store, and resources for accessing the configuration store to program the programmable execution unit. An instruction register is included in the data processor which holds a current instruction for execution, and is coupled to an instruction data path to supply the instruction to the defined instruction unit and to the programmable instruction units in parallel, through appropriate decoding resources. A RISA instruction page table is used to detect when an instruction in the sequence has not been configured for the RISAs on chip. When a RISA instruction page table miss is detected, the program is stopped and programmable execution unit configured with the new instruction. Techniques for compiling a program using both RISA and fixed instructions optimizes utilization of configurable resources in the system. Further, synthesis of RISA instructions can be carried out on the fly during the execution of other instructions by the system, or this synthesis can be done at compile time.

대표청구항 ▼

[ What is claimed is:] [1.] A data processor comprising:internal buses for operand and result data;a defined execution unit coupled to the internal buses for execution of defined instructions;a plurality of separately configurable execution units coupled to the internal buses for execution of respec

[ What is claimed is:] [1.] A data processor comprising:internal buses for operand and result data;a defined execution unit coupled to the internal buses for execution of defined instructions;a plurality of separately configurable execution units coupled to the internal buses for execution of respective sets of programmed instructions; anda condition code register connected to at least one of the configurable execution units to receive condition codes from said at least one of the configurable execution units.