[특허]Graphics accelerator chip and method

Graphics accelerator chip and method 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/00
출원번호	US-0429834 (1995-04-27)
발명자 / 주소	Becklund Thomas K. Houg Todd C. Jackson Benton H. Sluiter David O. Ukura John R.
출원인 / 주소	Control Systems, Inc.
대리인 / 주소	Merchant, Gould, Smith, Edell, Welter & Schmidt, P.A.
인용정보	피인용 횟수 : 92 인용 특허 : 0

초록 ▼

A graphics accelerator chip which interprets instructions and data transferred from a microprocessor via an external data bus logically coupled to the microprocessor. A host logic interface buffers the information received from the microprocessor with an on-chip first-in first-out (FIFO) memory which has an address space mapped onto a contiguous sequential address space of the microprocessor. A state machine having a temporary memory receives and interprets instructions and data from the FIFO memory, and routes them to a graphics register set which performs logical graphics operations based upon the graphics instructions and data. The temporary memory stores the last primitive command received, allowing the chip to perform multiple graphics operations where a primitive command is received from the microprocessor only once. A separate data bus from the host logic interface to the graphics register set enables direct access to the graphics registers from the microprocessor.

대표청구항 ▼

[ What is claimed is:] [1.] A graphics accelerator chip which interprets instructions and data transferred from a microprocessor via an external data bus logically coupled to the microprocessor, the graphics accelerator chip comprising:(a) a host logic interface logically coupled to the microprocessor via the external data bus for transferring the instructions and data between the graphics accelerator chip and the microprocessor;(b) a first-in first-out (FIFO) memory logically coupled to the host logic interface for receiving and buffering the instructions and data, wherein the FIFO memory address space is mapped onto a contiguous sequential address space of the microprocessor;(c) a state machine logically coupled to the FIFO memory for receiving and interpreting the instructions and data, and performing logical state operations based upon the instructions and data;(d) a temporary memory logically coupled to the state machine for temporarily storing a graphics instruction while the data associated with that graphics instruction is outputted from the FIFO memory; and(e) a graphics register set logically coupled to the state machine and the temporary memory via a first internal data bus, wherein the graphics register set receives and interprets the graphics instruction and data and performs logical graphics operations based upon the graphics instruction and data.

이 특허를 인용한 특허 (92)

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Graphics accelerator chip and method 원문보기

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Graphics accelerator chip and method 원문보기

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