[특허]Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA control

[미국특허] Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA control 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/00 G06F-013/38
출원번호	US-0650524 (1996-05-20)
발명자 / 주소	Swanstrom Scott
출원인 / 주소	Advanced Micro Devices
대리인 / 주소	Conley, Rose & TayonKivlin
인용정보	피인용 횟수 : 27 인용 특허 : 0

초록 ▼

A method for performing data transfers in a computer system comprising an improved DMA controller (DMAC) for performing DMA transfers between a peripheral device and system memory and receiving and servicing interrupts generated by the peripheral device. The system comprises a CPU, system memory, the DMA controller and a plurality of peripheral devices interconnected by buses. The CPU programs the peripheral, such as a disk drive, to retrieve or store data. When the peripheral has retrieved the data or is ready to receive the data the peripheral generates an interrupt. The CPU programs the DMAC to perform DMA transfers between the peripheral and the system memory and to selectively decouple the interrupt request from the peripheral to the CPU so that the DMAC can service the interrupt from the peripheral rather than the CPU. The decoupling is selectively performed so that, in the case of a write to the peripheral, the DMAC can receive the interrupt from the peripheral and perform the data transfer. In the case of a read from the peripheral, the DMAC performs the data transfer, then receives and services the interrupt from the peripheral. The CPU also programs the DMAC to selectively generate an interrupt to the CPU upon completion of DMA transfers. The CPU also programs the DMAC to selectively wait for an interrupt from the peripheral before performing the DMA transfers. The CPU also programs the DMAC to selectively poll for status in the peripheral and check for error conditions.

대표청구항 ▼

[ What is claimed is:] [1.] A method for performing a transfer of data in a computer system comprising one or more buses, a CPU having a CPU interrupt request input, a peripheral device having a peripheral interrupt request output, a system memory, and a programmable direct memory access (DMA) controller which improves the real-time characteristics of said computer system comprising:said CPU programming said DMA controller to start said transfer of said data and to generate an interrupt to said CPU upon completion of said transfer of said data;said DMA controller performing said transfer of said data in response to said CPU programming said DMA controller;said DMA controller decoupling said peripheral interrupt request output from said CPU interrupt request input in response to said CPU programming said DMA controller;said DMA controller generating said interrupt to said CPU to indicate said transfer of said data is complete in response to completion of said transfer of said data;said CPU clearing said interrupt; andsaid DMA controller coupling said peripheral interrupt request output to said CPU interrupt request input in response to said CPU clearing said interrupt.

이 특허를 인용한 특허 (27) 인용/피인용 타임라인 분석

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Hoerler, Johannes Markus; Sweet, Jr., Francis W.; Turner, Joseph, Method and apparatus for fast acknowledgement and efficient servicing of interrupt sources coupled to high latency paths.
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Davies, Ian Robert; Pecone, Victor Key, Method for adopting an orphan I/O port in a redundant storage controller.
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Jahnke, Steven R.; Hamakawa, Hiromichi, Micro-controller direct memory access (DMA) operation with adjustable word size transfers and address alignment/incrementing.
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Iwasaki Masaaki,JPX ; Nakamura Shouji,JPX ; Takeuchi Tadashi,JPX, Multimedia data transferring method.
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Iwasaki, Masaaki; Nakamura, Shouji; Takeuchi, Tadashi, Multimedia data transferring method.
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Dean A. Klein, Processor with internal register for peripheral status.
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Klein Dean A., Processor with internal register for peripheral status.
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Ashmore, Paul Andrew, Redundant storage controller system with enhanced failure analysis capability.
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Davies, Ian Robert, Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory.
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Davies, Ian Robert, System and method for sharing SATA drives in active-active RAID controller system.
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Sheikh Tahir Q. ; Wallach Walter A., System for data and interrupt posting for computer devices.
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Martwick Andrew, System for managing input/output accesses at a bridge/memory controller having a status register for recording cause of interrupt.
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[미국특허] Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA control 원문보기

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[미국특허] Method for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA control 원문보기

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